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Commit Graph

  • 3f2c55cb63 arch-riscv: Check RISCV process run in matched CPU Roger Chang 2023-01-09 14:04:06 +08:00
  • d6bbccb60a gpu-compute : Fix incorrect TLB stats when FunctionalTLB is used Vishnu Ramadas 2023-01-09 12:48:42 -06:00
  • 4e61a98336 mem-ruby: add GPU cache bypass I->I transition Matt Sinclair 2023-01-07 16:44:25 -06:00
  • 1d467bed7f mem-ruby: fix TCP spacing/spelling Matt Sinclair 2023-01-07 16:43:20 -06:00
  • 24e2ef0b78 mem-ruby, gpu-compute: fix TCP GLC cache bypassing Matt Sinclair 2023-01-07 16:01:57 -06:00
  • f89973c9e1 fastmodel: Add handler to catch DMI warnings Nicolas Boichat 2023-01-05 03:32:24 +00:00
  • 8aa9f52953 systemc: Add facilities to add extra SystemC message handlers Nicolas Boichat 2023-01-05 03:24:29 +00:00
  • 68cf65e9b5 scons: Clone env before modifying it in SharedLib Nicolas Boichat 2023-01-06 13:53:55 +00:00
  • ac54c7ffad cpu-o3: Resolve the skid buffer overflow issue at decode stage Hanhwi Jang 2023-01-05 14:52:11 +09:00
  • c23d7bb3ee gpu-compute, mem-ruby: Add p_popRequestQueue to some transitions Vishnu Ramadas 2023-01-04 21:34:17 -06:00
  • ddf43726ef gpu-compute, mem-ruby: Update GPU cache bypassing to use TBE Vishnu Ramadas 2023-01-04 21:07:54 -06:00
  • 03083ba5e3 arch-vega: Implement ds_write2st64_b64 Matthew Poremba 2022-12-26 16:46:40 -08:00
  • 450bc254bd arch-vega: Read one dword for SGPR base global insts Matthew Poremba 2022-12-26 15:08:23 -08:00
  • 3bfa220e4e arch-vega: Implement ds_read_i8 Matthew Poremba 2022-12-26 13:27:06 -08:00
  • b83457df0b arch-vega: Implement ds_add_u64 Matthew Poremba 2022-12-26 09:54:20 -08:00
  • 892e3057f7 arch-vega: Implement ds_add_f32 atomic Matthew Poremba 2022-12-26 09:13:06 -08:00
  • 160815f482 base: Specialize bitwise atomics so FP types can be used Matthew Poremba 2022-12-26 09:18:49 -08:00
  • 7238df7859 util: Update run_gem5_fs.sh script with AArch64 platform Giacomo Travaglini 2022-12-20 08:43:59 +00:00
  • a533cb246c scons: Include libraries when building gem5 as a shared object Giacomo Travaglini 2022-12-19 16:08:29 +00:00
  • 15cb9c7abe base: socket: add UnixSocketAddr for representing socket paths Simon Park 2023-01-03 01:07:03 -08:00
  • 313f557b93 ext-testlib: Support str-convertible args in gem5_verify_config Gabriel Busnot 2023-01-03 15:37:38 +00:00
  • 5357277039 ext-testlib: Improve error reporting when test definition fails Gabriel Busnot 2023-01-03 15:33:44 +00:00
  • 49ac00d060 stdlib: Fix errors in MESI_Three_Level_Cache_Hierarchy Hoa Nguyen 2022-12-17 09:02:50 +00:00
  • 022a48f9f6 arch-vega: Implement ds_add_u32 atomic Matthew Poremba 2022-12-26 09:11:14 -08:00
  • e392603d81 arch-vega: Add missing operand size for ds_write2st64_b64 Matthew Poremba 2022-12-26 09:08:25 -08:00
  • 6449633827 arch-vega: Add DPP support for V_AND_B32 Matthew Poremba 2022-12-16 13:39:24 -08:00
  • bbdebc25da arch-vega: Fix several issues with DPP Matthew Poremba 2022-12-16 13:35:02 -08:00
  • f99a3c1f96 arch-vega: Fix signed BFE instructions Matthew Poremba 2022-12-16 13:23:01 -08:00
  • bbeec2d758 misc: Update version info for develop branch Bobby R. Bruce 2022-12-30 20:28:55 +00:00
  • 28a871b037 scons: Re-add -Werror for gem5 develop branch Bobby R. Bruce 2022-12-30 20:11:43 +00:00
  • 1d038cc77d Merge "misc: Merge branch stable into develop branch" into develop Bobby Bruce 2023-01-03 22:08:08 +00:00
  • 66d4a15820 gpu-compute,mem-ruby: Add support for GPU cache bypassing Vishnu Ramadas 2022-12-26 19:14:11 -06:00
  • 5db889572a base: Remove unused output.hh dependency from trace.cc Rocky Tatiefo 2022-12-29 20:11:08 -08:00
  • 083566d0c8 arch-riscv: add RV32 ADFIMU_Zfh instruction tests Roger Chang 2022-12-09 10:31:50 +08:00
  • 218b3925be misc: Merge branch stable into develop branch Bobby R. Bruce 2022-12-30 20:06:49 +00:00
  • 5fa484e2e0 misc: Merge the v22.1 release staging into stable Bobby R. Bruce 2022-12-30 19:53:52 +00:00
  • 61aabd516e misc: Update RELEASE-NOTES.md for v22.1.0.0 Bobby R. Bruce 2022-12-02 11:28:15 -08:00
  • fcde59b245 util: ext/systemc is importing env Environment instead of main Giacomo Travaglini 2022-12-19 17:09:28 +00:00
  • 55fb8bf40e util: Update util-tlm to require C++17 Giacomo Travaglini 2022-12-19 16:06:13 +00:00
  • 25b4defa6a util: Fix missing include of sim/core.hh in util-tlm Giacomo Travaglini 2022-12-19 16:00:34 +00:00
  • 8d117aad71 util: cxxConfigInit has been removed by gem5 Giacomo Travaglini 2022-12-19 15:56:49 +00:00
  • 9cd61d000a arch-riscv: Correct the IllegalInstFault messege of instruction c.addi4spn Roger Chang 2022-12-23 10:05:46 +08:00
  • 9ce8c9b81c arch-riscv: Refactor template JumpConstructor Roger Chang 2022-12-19 14:08:22 +08:00
  • 6797c78942 arch-riscv: Refactor compressed instructions Roger Chang 2022-12-16 13:27:14 +08:00
  • 5447d55e39 dev: Fix -Wunused-variable in structured binding Giacomo Travaglini 2022-12-21 09:00:30 +00:00
  • 7fb2fda841 base: Fix signature of SatCounter::saturate() Daniel R. Carvalho 2022-12-18 10:33:10 -03:00
  • 06f18242fe tests: Fix compiler-tests.sh build args passing Bobby R. Bruce 2022-12-17 03:11:53 -08:00
  • 55d8219717 tests: Remove get_runtime_isa() from parsec_disk_run.py Melissa Jost 2022-12-09 16:17:25 -08:00
  • 4cae2ae4ad tests: Remove get_runtime_isa() from parsec_disk_run.py Melissa Jost 2022-12-09 16:17:25 -08:00
  • af2cecf59e gpu-compute: Fix ABI init for DispatchId Matthew Poremba 2022-12-15 11:43:01 -08:00
  • fbd0722de4 fastmodel,dev: Replace the reset port with a Signal*Port<bool>. Gabe Black 2022-12-13 02:17:22 -08:00
  • 0aaaa6b4ae fastmodel: Change the Signal proxies to use Signal*Port<bool>. Gabe Black 2022-12-13 00:32:08 -08:00
  • 89d5bfca7c fastmodel,dev: Rework the Int*Pin classes with Signal*Port. Gabe Black 2022-12-12 23:59:21 -08:00
  • 7a21ecf15c dev: Implement a "Signal" port which has a templated State type. Gabe Black 2022-12-12 23:51:14 -08:00
  • 8b1688da34 dev: Introduce a reset() method on RegisterBank and Register classes. Gabe Black 2022-12-10 02:29:43 -08:00
  • f96513fd04 sim,sim-se: Fix restoring of VMAs of memory-mapped files Emin Gadzhiev 2022-12-02 02:18:44 +03:00
  • f7d0808a5c arch-riscv: Fork Zba, Zbb, Zbc, Zbs instructions into rv32 / rv64 Roger Chang 2022-11-30 16:36:05 +08:00
  • 2ed4323899 tests: Fix compiler-tests.sh for no build args passed case Bobby R. Bruce 2022-12-12 13:52:22 -08:00
  • ad107116a1 arch-riscv: Support RV32 to remote gdb Roger Chang 2022-11-28 08:28:12 +00:00
  • dd04e70445 arch-riscv: Implement rv32 zicsr extension Roger Chang 2022-11-28 08:27:48 +00:00
  • fa34ebc853 arch-riscv: Fork ACDFIMU_Zfh instructions into rv32/rv64 Roger Chang 2022-11-29 16:18:22 +08:00
  • d65173d596 tests: Move replacement policy tests to long/Nightly Bobby R. Bruce 2022-12-10 15:56:02 -08:00
  • ce03482a39 mem: Implement and use the recvMemBackdoorReq func. Yu-hsin Wang 2022-12-08 17:03:49 +08:00
  • 91f8f2b276 tests: Add missing _pre_instantiate() Bobby R. Bruce 2022-12-02 11:15:45 -08:00
  • 81cb7c05b4 misc: Update .mailmap Bobby R. Bruce 2022-12-06 14:13:40 -08:00
  • 1b2252cbc0 misc: Update .mailmap Bobby R. Bruce 2022-12-06 14:13:40 -08:00
  • bd31956060 tests: Add replacement policy tests Jarvis 2022-12-07 11:18:30 -06:00
  • e81aa1cd86 configs: Alter x86-npb-benchmarks.py to exit after WORKEND Bobby R. Bruce 2022-12-06 10:48:48 -08:00
  • a23641e01f configs: Fix x86-gapbs-benchmarks.py example Bobby R. Bruce 2022-12-06 10:39:18 -08:00
  • c765cfb64b configs: Alter x86-npb-benchmarks.py to exit after WORKEND Bobby R. Bruce 2022-12-06 10:48:48 -08:00
  • 5d475506d7 configs: Fix x86-gapbs-benchmarks.py example Bobby R. Bruce 2022-12-06 10:39:18 -08:00
  • 00a893ad4e systemc: Enable DMI in the non-blocking/timing mode bridge. Gabe Black 2022-10-04 05:36:22 -07:00
  • 985d9c641f systemc: replace the deprecated std::iterator Yu-hsin Wang 2022-12-02 16:27:16 +08:00
  • 1e73beb620 python: Remove 'scheduleTickExit' in favor of 'exitSimLoop' Bobby R. Bruce 2022-12-05 15:28:00 -08:00
  • ae20719576 python: Remove 'scheduleTickExit' in favor of 'exitSimLoop' Bobby R. Bruce 2022-12-05 15:28:00 -08:00
  • 9d1cc1bcc9 dev: Add an offset checking mechanism to RegisterBank. Gabe Black 2022-12-05 05:03:53 -08:00
  • b9c0851120 systemc: fix the payload and packet association in Gem5ToTlm bridge Yu-hsin Wang 2022-11-23 17:13:49 +08:00
  • 4fc690f6b7 mem-cache: Fix FIFO replacement Jarvis Jia 2022-11-23 15:11:16 -06:00
  • e200ea1510 ext: Update ext/sst/README.md for v22.1 release Bobby R. Bruce 2022-11-21 16:11:07 -08:00
  • 620e5243e7 tests: Update presubmit.sh to use v22-1 docker images Bobby R. Bruce 2022-11-21 16:07:44 -08:00
  • a3fd9631cc util-gem5art: Fix incorrect type of size in createArtifact Bobby R. Bruce 2022-12-02 11:15:45 -08:00
  • 1c422628bc tests: Update weekly test docker image tags to v22-1 Bobby R. Bruce 2022-11-21 16:04:02 -08:00
  • 38778c5a17 tests: Abstract the docker image tag for Weekly tests Bobby R. Bruce 2022-11-21 16:00:28 -08:00
  • 1e5bd5b89a tests: Update nightly test docker image tags to v22-1 Bobby R. Bruce 2022-11-21 15:56:06 -08:00
  • 1c79a469ba tests: Abstract the docker image tag for Nightly tests Bobby R. Bruce 2022-11-21 15:52:47 -08:00
  • d1c72cecb3 tests: Update the compiler-tests.sh to use the v22-1 images Bobby R. Bruce 2022-11-21 15:27:55 -08:00
  • ed6d80c273 util-docker: Add v22-1 tag to docker-compose.yaml Bobby R. Bruce 2022-11-22 13:44:31 -08:00
  • 3df8be981b util-docker: Update gcn-gpu Docker to use v22-1 ROCM patch Bobby R. Bruce 2022-11-22 13:40:56 -08:00
  • 7185c9ea19 stdlib: Update the gem5 resources' version to "v22.1" Bobby R. Bruce 2022-11-21 15:14:10 -08:00
  • da2c70af6f python,tests: Update Resource URL path to v22-1 Bobby R. Bruce 2022-11-21 13:54:20 -08:00
  • 363d65206a base: Update the version to v22.1.0.0 Bobby R. Bruce 2022-11-21 13:52:41 -08:00
  • 7dd61c8659 scons: Remove -Werror for the gem5 v22.1 release Bobby R. Bruce 2022-11-21 13:48:29 -08:00
  • 23a406e811 arch-arm: Setup TC/ISA at construction time 2nd attempt Giacomo Travaglini 2022-11-23 08:35:50 +00:00
  • 596da56b61 arch-arm: Remove deprecated Armv7 debug Vector Catch Giacomo Travaglini 2022-12-01 11:37:14 +00:00
  • ed6cf2eced dev-arm: Allow GICv3 to be externally(publicly) updated Giacomo Travaglini 2022-11-01 17:43:35 +00:00
  • 0df37a33f6 arch-arm: Setup TC/ISA at construction time 2nd attempt Giacomo Travaglini 2022-11-23 08:35:50 +00:00
  • 749c4779f4 arch-riscv: Add basic features toward rv32 support Roger Chang 2022-11-28 07:21:14 +00:00
  • 6f3f6c16f3 stdlib, configs: Updating configs/example/gem5_library Melissa Jost 2022-10-18 16:04:18 -07:00
  • 005049f548 stdlib,python: Allow setting of to tick exits via m5 Bobby R. Bruce 2022-11-30 15:02:05 -08:00
  • da83764f94 stdlib, configs: Updating configs/example/gem5_library Melissa Jost 2022-10-18 16:04:18 -07:00