arch-riscv: Fork ACDFIMU_Zfh instructions into rv32/rv64

1. Add rvSelect for rv32 and rv64.
2. Add rvZext and rvSext for rv32 handle sign extension
3. Fork the following instructions into rv32/rv64 version

A extensions:
SC.W
LR.D
SC.D
AMOADD.D
AMOSWAP.D
AMOXOR.D
AMOOR.D
AMOAND.D
AMOMIN.D
AMOMAX.D
AMOMINU.D
AMOMAXU.D

C extensions:
C.ADDI4SPN
C.FLD
C.LW
C.FLW
C.LD
C.FSD
C.SW
C.FSW
C.SD
C.ADDI
C.JAL
C.ADDIW
C.ADDI16SP
C.SRLI
C.SRAI
C.ANDI
C.SUB
C.XOR
C.OR
C.AND
C.SUBW
C.ADDW
C.J
C.BEQZ
C.BNEZ
C.SLLI
C.FLDSP
C.LWSP
C.FLWSP
C.LDSP
C.JR
C.MV
C.EBREAK
C.JALR
C.ADD
C.FSDSP
C.SWSP
C.FSWSP
C.SDSPF

D extensions:
FCVT.L.D
FCVT.LU.D
FCVT.D.L
FCVT.D.LU
FMV.X.D
FCLASS.D
FMV.D.X

F extensions:
FSW
FCVT.L.S
FCVT.LU.S
FCVT.S.W
FCVT.S.WU
FCVT.S.L
FCVT.S.LU
FMV.X.W
FCLASS.S
FMV.W.X

I extensions:
LD
LWU
SLLI
ADDI
SLTI
SLTIU
XORI
SRLI
SRAI
ORI
ANDI
AUIPC
ADDIW
SLLIW
SRLIW
SRAIW
SD
ADD
SUB
SLL
SLT
SLTU
XOR
SRL
SRA
OR
AND
LUI
BEQ
BNE
BLT
BGE
BLTU
BGEU
JALR
JAL
ADDW
SUBW
SLLW
SRLW
SRAW

M extensions:
MUL
MULH
MULHSU
MULHU
DIV
DIVU
REM
REMU
MULW
DIVW
DIVUW
REMW
REMUW

ZFH extensions:
FSH
FCVT.L.H
FCVT.LU.H
FCVT.H.L
FCVT.H.LU

Change-Id: I8604324eadb700591db028aa3b013b060ba37de5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65111
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/riscv/insts/static_inst.hh

@@ -58,6 +58,18 @@ class RiscvStaticInst : public StaticInst
 
     bool alignmentOk(ExecContext* xc, Addr addr, Addr size) const;
 
+    template <typename T>
+    T
+    rvSelect(T v32, T v64) const
+    {
+        return (machInst.rv_type == RV32) ? v32 : v64;
+    }
+
+    template <typename T32, typename T64>
+    T64 rvExt(T64 x) const { return rvSelect((T64)(T32)x, x); }
+    uint64_t rvZext(uint64_t x) const { return rvExt<uint32_t, uint64_t>(x); }
+    int64_t rvSext(int64_t x) const { return rvExt<int32_t, int64_t>(x); }
+
   public:
     ExtMachInst machInst;
 

src/arch/riscv/isa/bitfields.isa

@@ -3,6 +3,7 @@
 // Copyright (c) 2015 RISC-V Foundation
 // Copyright (c) 2016 The University of Virginia
 // Copyright (c) 2020 Barkhausen Institut
+// Copyright (c) 2022 Google LLC
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -49,6 +50,7 @@ def bitfield FUNCT7 <31:25>;
 def bitfield SRTYPE <30>;
 def bitfield SHAMT5 <24:20>;
 def bitfield SHAMT6 <25:20>;
+def bitfield SHAMT6BIT5 <25>;
 
 // I-Type
 def bitfield IMM12  <31:20>;

src/arch/riscv/isa/formats/amo.isa

@@ -446,8 +446,8 @@ def template AtomicMemOpRMWCompleteAcc {{
 
 // LR/SC/AMO decode formats
 
-def format LoadReserved(memacc_code, postacc_code={{ }}, ea_code={{EA = Rs1;}},
-        mem_flags=[], inst_flags=[]) {{
+def format LoadReserved(memacc_code, postacc_code={{ }},
+        ea_code={{EA = rvZext(Rs1);}}, mem_flags=[], inst_flags=[]) {{
     macro_ea_code = ''
     macro_inst_flags = []
     macro_iop = InstObjParams(name, Name, 'LoadReserved', macro_ea_code,
@@ -473,8 +473,8 @@ def format LoadReserved(memacc_code, postacc_code={{ }}, ea_code={{EA = Rs1;}},
         + LoadReservedCompleteAcc.subst(iop)
 }};
 
-def format StoreCond(memacc_code, postacc_code={{ }}, ea_code={{EA = Rs1;}},
-        mem_flags=[], inst_flags=[]) {{
+def format StoreCond(memacc_code, postacc_code={{ }},
+        ea_code={{EA = rvZext(Rs1);}}, mem_flags=[], inst_flags=[]) {{
     macro_ea_code = ''
     macro_inst_flags = []
     macro_iop = InstObjParams(name, Name, 'StoreCond', macro_ea_code,
@@ -501,7 +501,7 @@ def format StoreCond(memacc_code, postacc_code={{ }}, ea_code={{EA = Rs1;}},
 }};
 
 def format AtomicMemOp(memacc_code, amoop_code, postacc_code={{ }},
-        ea_code={{EA = Rs1;}}, mem_flags=[], inst_flags=[]) {{
+        ea_code={{EA = rvZext(Rs1);}}, mem_flags=[], inst_flags=[]) {{
     macro_ea_code = ''
     macro_inst_flags = []
     macro_iop = InstObjParams(name, Name, 'AtomicMemOp', macro_ea_code,

src/arch/riscv/isa/formats/mem.isa

@@ -228,7 +228,7 @@ def template StoreCompleteAcc {{
     }
 }};
 
-def format Load(memacc_code, ea_code = {{EA = Rs1 + offset;}},
+def format Load(memacc_code, ea_code = {{EA = rvZext(Rs1 + offset);}},
         offset_code={{offset = sext<12>(IMM12);}},
         mem_flags=[], inst_flags=[]) {{
     (header_output, decoder_output, decode_block, exec_output) = \
@@ -236,7 +236,7 @@ def format Load(memacc_code, ea_code = {{EA = Rs1 + offset;}},
         inst_flags, 'Load', exec_template_base='Load')
 }};
 
-def format Store(memacc_code, ea_code={{EA = Rs1 + offset;}},
+def format Store(memacc_code, ea_code={{EA = rvZext(Rs1 + offset);}},
         offset_code={{offset = sext<12>(IMM5 | (IMM7 << 5));}},
         mem_flags=[], inst_flags=[]) {{
     (header_output, decoder_output, decode_block, exec_output) = \