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arch-vega: Read one dword for SGPR base global insts

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Global instructions in Vega can either use a VGPR base address plus
instruction offset or SGPR base address plus VGPR offset plus
instruction offset. Currently the VGPR address/offset is always read as
two dwords. This causes problems if the VGPR number is the last VGPR
allocated to a wavefront since the second dword would be beyond the
allocation and trip an assert.

This changeset sets the operand size of the VGPR operand to one dword
when SGPR base is used and two dwords otherwise so initDynOperandInfo
does not assert. It also moves the read of the VGPR into the calcAddr
method so that the correct ConstVecOperandU## is used to prevent another
assertion failure when reading from the register file. These two changes
are made to all flat instructions, as global instructions are a
subsegement of flat instructions.

Change-Id: I79030771aa6deec05ffa5853ca2d8b68943ee0a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67077
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Matthew Poremba
2022-12-26 15:08:23 -08:00
parent 3bfa220e4e
commit 450bc254bd
3 changed files with 73 additions and 107 deletions
Download Patch File Download Diff File Expand all files Collapse all files

80
src/arch/amdgpu/vega/insts/instructions.cc
View File

@@ -43831,11 +43831,7 @@ namespace VegaISA
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
addr.read();
calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET);
calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
issueRequestHelper(gpuDynInst);
} // execute
@@ -43919,11 +43915,7 @@ namespace VegaISA
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
addr.read();
calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET);
calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
issueRequestHelper(gpuDynInst);
} // execute
@@ -44008,11 +44000,7 @@ namespace VegaISA
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
addr.read();
calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET);
calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
issueRequestHelper(gpuDynInst);
} // execute
@@ -44067,11 +44055,7 @@ namespace VegaISA
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
addr.read();
calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET);
calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
issueRequestHelper(gpuDynInst);
} // execute
@@ -44126,11 +44110,7 @@ namespace VegaISA
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
addr.read();
calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET);
calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
issueRequestHelper(gpuDynInst);
} // execute
@@ -44194,11 +44174,7 @@ namespace VegaISA
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
addr.read();
calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET);
calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
issueRequestHelper(gpuDynInst);
} // execute
@@ -44266,13 +44242,11 @@ namespace VegaISA
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
ConstVecOperandU8 data(gpuDynInst, extData.DATA);
addr.read();
data.read();
calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET);
calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
@@ -44325,13 +44299,11 @@ namespace VegaISA
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
ConstVecOperandU16 data(gpuDynInst, extData.DATA);
addr.read();
data.read();
calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET);
calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
@@ -44384,13 +44356,11 @@ namespace VegaISA
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
ConstVecOperandU32 data(gpuDynInst, extData.DATA);
addr.read();
data.read();
calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET);
calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
@@ -44444,13 +44414,11 @@ namespace VegaISA
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
ConstVecOperandU64 data(gpuDynInst, extData.DATA);
addr.read();
data.read();
calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET);
calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
@@ -44504,17 +44472,15 @@ namespace VegaISA
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
ConstVecOperandU32 data0(gpuDynInst, extData.DATA);
ConstVecOperandU32 data1(gpuDynInst, extData.DATA + 1);
ConstVecOperandU32 data2(gpuDynInst, extData.DATA + 2);
addr.read();
data0.read();
data1.read();
data2.read();
calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET);
calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
@@ -44572,19 +44538,17 @@ namespace VegaISA
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
ConstVecOperandU32 data0(gpuDynInst, extData.DATA);
ConstVecOperandU32 data1(gpuDynInst, extData.DATA + 1);
ConstVecOperandU32 data2(gpuDynInst, extData.DATA + 2);
ConstVecOperandU32 data3(gpuDynInst, extData.DATA + 3);
addr.read();
data0.read();
data1.read();
data2.read();
data3.read();
calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET);
calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
@@ -44650,13 +44614,11 @@ namespace VegaISA
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
ConstVecOperandU32 data(gpuDynInst, extData.DATA);
addr.read();
data.read();
calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET);
calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
@@ -44732,15 +44694,13 @@ namespace VegaISA
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
ConstVecOperandU32 data(gpuDynInst, extData.DATA);
ConstVecOperandU32 cmp(gpuDynInst, extData.DATA + 1);
addr.read();
data.read();
cmp.read();
calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET);
calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
@@ -44814,13 +44774,11 @@ namespace VegaISA
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
ConstVecOperandU32 data(gpuDynInst, extData.DATA);
addr.read();
data.read();
calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET);
calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
@@ -45204,15 +45162,13 @@ namespace VegaISA
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
ConstVecOperandU64 data(gpuDynInst, extData.DATA);
ConstVecOperandU64 cmp(gpuDynInst, extData.DATA + 2);
addr.read();
data.read();
cmp.read();
calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET);
calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
@@ -45287,13 +45243,11 @@ namespace VegaISA
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
ConstVecOperandU64 data(gpuDynInst, extData.DATA);
addr.read();
data.read();
calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET);
calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {

80
src/arch/amdgpu/vega/insts/instructions.hh
View File

@@ -41892,7 +41892,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_dst or saddr
return isFlat() ? 1 : 8;
case 2: //vgpr_dst
@@ -41929,7 +41929,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_dst or saddr
return isFlat() ? 1 : 8;
case 2: //vgpr_dst
@@ -41966,7 +41966,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_dst or saddr
return isFlat() ? 2 : 8;
case 2: //vgpr_dst
@@ -42003,7 +42003,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_dst or saddr
return isFlat() ? 2 : 8;
case 2: //vgpr_dst
@@ -42040,7 +42040,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_dst or saddr
return isFlat() ? 4 : 8;
case 2: //vgpr_dst
@@ -42077,7 +42077,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_dst or saddr
return isFlat() ? 8 : 8;
case 2: //vgpr_dst
@@ -42114,7 +42114,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_dst or saddr
return isFlat() ? 12 : 8;
case 2: //vgpr_dst
@@ -42151,7 +42151,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_dst or saddr
return isFlat() ? 16 : 8;
case 2: //vgpr_dst
@@ -42188,7 +42188,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 1;
case 2: //saddr
@@ -42225,7 +42225,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 2;
case 2: //saddr
@@ -42262,7 +42262,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 4;
case 2: //saddr
@@ -42299,7 +42299,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 8;
case 2: //saddr
@@ -42336,7 +42336,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 12;
case 2: //saddr
@@ -42373,7 +42373,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 16;
case 2: //saddr
@@ -42410,7 +42410,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 4;
case 2: //vgpr_dst or saddr
@@ -42449,7 +42449,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 8;
case 2: //vgpr_dst or saddr
@@ -42488,7 +42488,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 4;
case 2: //vgpr_dst or saddr
@@ -42527,7 +42527,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 4;
case 2: //vgpr_dst or saddr
@@ -42564,7 +42564,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 4;
case 2: //vgpr_dst or saddr
@@ -42601,7 +42601,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 4;
case 2: //vgpr_dst or saddr
@@ -42638,7 +42638,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 4;
case 2: //vgpr_dst or saddr
@@ -42675,7 +42675,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 4;
case 2: //vgpr_dst or saddr
@@ -42712,7 +42712,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 4;
case 2: //vgpr_dst or saddr
@@ -42749,7 +42749,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 4;
case 2: //vgpr_dst or saddr
@@ -42786,7 +42786,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 4;
case 2: //vgpr_dst or saddr
@@ -42823,7 +42823,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 4;
case 2: //vgpr_dst or saddr
@@ -42860,7 +42860,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 4;
case 2: //vgpr_dst or saddr
@@ -42897,7 +42897,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 8;
case 2: //vgpr_dst or saddr
@@ -42934,7 +42934,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 16;
case 2: //vgpr_dst or saddr
@@ -42973,7 +42973,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 8;
case 2: //vgpr_dst or saddr
@@ -43012,7 +43012,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 8;
case 2: //vgpr_dst or saddr
@@ -43049,7 +43049,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 8;
case 2: //vgpr_dst or saddr
@@ -43086,7 +43086,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 8;
case 2: //vgpr_dst or saddr
@@ -43123,7 +43123,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 8;
case 2: //vgpr_dst or saddr
@@ -43160,7 +43160,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 8;
case 2: //vgpr_dst or saddr
@@ -43197,7 +43197,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 8;
case 2: //vgpr_dst or saddr
@@ -43234,7 +43234,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 8;
case 2: //vgpr_dst or saddr
@@ -43271,7 +43271,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 8;
case 2: //vgpr_dst or saddr
@@ -43308,7 +43308,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 8;
case 2: //vgpr_dst or saddr
@@ -43345,7 +43345,7 @@ namespace VegaISA
{
switch (opIdx) {
case 0: //vgpr_addr
return 8;
return vgprIsOffset() ? 4 : 8;
case 1: //vgpr_src
return 8;
case 2: //vgpr_dst or saddr

20
src/arch/amdgpu/vega/insts/op_encodings.hh
View File

@@ -925,7 +925,7 @@ namespace VegaISA
}
void
calcAddr(GPUDynInstPtr gpuDynInst, ConstVecOperandU64 &vaddr,
calcAddr(GPUDynInstPtr gpuDynInst, ScalarRegU32 vaddr,
ScalarRegU32 saddr, ScalarRegI32 offset)
{
// Offset is a 13-bit field w/the following meanings:
@@ -940,14 +940,20 @@ namespace VegaISA
// be a 64-bit address. Otherwise, saddr is the reg index for a
// scalar reg used as the base address for a 32-bit address.
if ((saddr == 0x7f && isFlatGlobal()) || isFlat()) {
calcAddrVgpr(gpuDynInst, vaddr, offset);
ConstVecOperandU64 vbase(gpuDynInst, vaddr);
vbase.read();
calcAddrVgpr(gpuDynInst, vbase, offset);
} else {
// Assume we are operating in 64-bit mode and read a pair of
// SGPRs for the address base.
ConstScalarOperandU64 sbase(gpuDynInst, saddr);
sbase.read();
calcAddrSgpr(gpuDynInst, vaddr, sbase, offset);
ConstVecOperandU32 voffset(gpuDynInst, vaddr);
voffset.read();
calcAddrSgpr(gpuDynInst, voffset, sbase, offset);
}
if (isFlat()) {
@@ -974,6 +980,12 @@ namespace VegaISA
}
}
bool
vgprIsOffset()
{
return (extData.SADDR != 0x7f);
}
// first instruction DWORD
InFmt_FLAT instData;
// second instruction DWORD
@@ -987,7 +999,7 @@ namespace VegaISA
void generateGlobalDisassembly();
void
calcAddrSgpr(GPUDynInstPtr gpuDynInst, ConstVecOperandU64 &vaddr,
calcAddrSgpr(GPUDynInstPtr gpuDynInst, ConstVecOperandU32 &vaddr,
ConstScalarOperandU64 &saddr, ScalarRegI32 offset)
{
// Use SGPR pair as a base address and add VGPR-offset and