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arch-vega: Implement ds_write2st64_b64

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Write two qwords at offsets multiplied by 8 * 64 bytes.

Change-Id: I0d0e05f3e848c2fd02d32095e32b7f023bd8803b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67078
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
This commit is contained in:
Matthew Poremba
2022-12-26 16:46:40 -08:00
parent 450bc254bd
commit 03083ba5e3
2 changed files with 47 additions and 1 deletions
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46
src/arch/amdgpu/vega/insts/instructions.cc
View File

@@ -36595,8 +36595,52 @@ namespace VegaISA
void
Inst_DS__DS_WRITE2ST64_B64::execute(GPUDynInstPtr gpuDynInst)
{
panicUnimplemented();
Wavefront *wf = gpuDynInst->wavefront();
if (gpuDynInst->exec_mask.none()) {
wf->decLGKMInstsIssued();
return;
}
gpuDynInst->execUnitId = wf->execUnitId;
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(
gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
ConstVecOperandU64 data0(gpuDynInst, extData.DATA0);
ConstVecOperandU64 data1(gpuDynInst, extData.DATA1);
addr.read();
data0.read();
data1.read();
calcAddr(gpuDynInst, addr);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
(reinterpret_cast<VecElemU64*>(
gpuDynInst->d_data))[lane * 2] = data0[lane];
(reinterpret_cast<VecElemU64*>(
gpuDynInst->d_data))[lane * 2 + 1] = data1[lane];
}
}
gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
} // execute
void
Inst_DS__DS_WRITE2ST64_B64::initiateAcc(GPUDynInstPtr gpuDynInst)
{
Addr offset0 = instData.OFFSET0 * 8 * 64;
Addr offset1 = instData.OFFSET1 * 8 * 64;
initDualMemWrite<VecElemU64>(gpuDynInst, offset0, offset1);
}
void
Inst_DS__DS_WRITE2ST64_B64::completeAcc(GPUDynInstPtr gpuDynInst)
{
}
// --- Inst_DS__DS_CMPST_B64 class methods ---
Inst_DS__DS_CMPST_B64::Inst_DS__DS_CMPST_B64(InFmt_DS *iFmt)

2
src/arch/amdgpu/vega/insts/instructions.hh
View File

@@ -33572,6 +33572,8 @@ namespace VegaISA
} // getOperandSize
void execute(GPUDynInstPtr) override;
void initiateAcc(GPUDynInstPtr) override;
void completeAcc(GPUDynInstPtr) override;
}; // Inst_DS__DS_WRITE2ST64_B64
class Inst_DS__DS_CMPST_B64 : public Inst_DS