derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-riscv: Check RISCV process run in matched CPU

Browse Source 
1. Remove set RV32 flag in RiscvProcess32
2. Check if binary run appropriate CPU

Change-Id: I00b0725f3eb4f29e45b8ec719317af79355dc728
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67251
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Roger Chang
2023-01-09 14:04:06 +08:00
parent d6bbccb60a
commit 3f2c55cb63
1 changed files with 8 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/arch/riscv/process.cc
View File

@@ -101,8 +101,12 @@ RiscvProcess64::initState()
Process::initState();
argsInit<uint64_t>(PageBytes);
for (ContextID ctx: contextIds)
system->threads[ctx]->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
for (ContextID ctx: contextIds) {
auto *tc = system->threads[ctx];
tc->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
auto *isa = dynamic_cast<ISA*>(tc->getIsaPtr());
fatal_if(isa->rvType() != RV64, "RISC V CPU should run in 64 bits mode");
}
}
void
@@ -114,9 +118,8 @@ RiscvProcess32::initState()
for (ContextID ctx: contextIds) {
auto *tc = system->threads[ctx];
tc->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
PCState pc = tc->pcState().as<PCState>();
pc.rvType(RV32);
tc->pcState(pc);
auto *isa = dynamic_cast<ISA*>(tc->getIsaPtr());
fatal_if(isa->rvType() != RV32, "RISC V CPU should run in 32 bits mode");
}
}