From 3f2c55cb63adfe702c8f6b30f879ae3c926d0a9a Mon Sep 17 00:00:00 2001
From: Roger Chang <rogerycchang@google.com>
Date: Mon, 9 Jan 2023 14:04:06 +0800
Subject: [PATCH] arch-riscv: Check RISCV process run in matched CPU

1. Remove set RV32 flag in RiscvProcess32
2. Check if binary run appropriate CPU

Change-Id: I00b0725f3eb4f29e45b8ec719317af79355dc728
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67251
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/riscv/process.cc | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index dc7abae790..cd00f5d63a 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -101,8 +101,12 @@ RiscvProcess64::initState()
     Process::initState();
 
     argsInit<uint64_t>(PageBytes);
-    for (ContextID ctx: contextIds)
-        system->threads[ctx]->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
+    for (ContextID ctx: contextIds) {
+        auto *tc = system->threads[ctx];
+        tc->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
+        auto *isa = dynamic_cast<ISA*>(tc->getIsaPtr());
+        fatal_if(isa->rvType() != RV64, "RISC V CPU should run in 64 bits mode");
+    }
 }
 
 void
@@ -114,9 +118,8 @@ RiscvProcess32::initState()
     for (ContextID ctx: contextIds) {
         auto *tc = system->threads[ctx];
         tc->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
-        PCState pc = tc->pcState().as<PCState>();
-        pc.rvType(RV32);
-        tc->pcState(pc);
+        auto *isa = dynamic_cast<ISA*>(tc->getIsaPtr());
+        fatal_if(isa->rvType() != RV32, "RISC V CPU should run in 32 bits mode");
     }
 }