arch-riscv: Correct the IllegalInstFault messege of instruction

c.addi4spn

In Riscv Manual Volumn I: Unpriviledged ISA section 18.5, c.addi4spn
will not working if imm == 0, not machInst == 0. It is changed in the
https://gem5-review.git.corp.google.com/c/public/gem5/+/66732, and here is the additional patch to the CL.

Change-Id: I2a3c9660dc43f1399f68e03c4f59207f869807a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66931
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/riscv/isa/decoder.isa

@@ -48,7 +48,7 @@ decode QUADRANT default Unknown::unknown() {
                   CIMM8<5:2> << 6;
         }}, {{
             if (imm == 0)
-                return std::make_shared<IllegalInstFault>("zero instruction",
+                return std::make_shared<IllegalInstFault>("immediate = 0",
                                                            machInst);
             Rp2 = rvSext(sp + imm);
         }}, uint64_t);