mem-ruby: add GPU cache bypass I->I transition

66d4a158 added support for AMD's GPU cache bypassing flags (GLC
for bypassing L1 caches, SLC for bypassing all caches).  However,
it did not add a transition for the situation where the cache line
is currently I (Invalid).  This commit adds this support, which
resolves an assert failure in Pannotia workloads when this situation
arises.

Change-Id: I59a62ce70c01dd8b73aacb733fb3d1d0dab2624b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67201
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

src/mem/ruby/protocol/GPU_VIPER-TCP.sm

@@ -619,6 +619,15 @@ machine(MachineType:TCP, "GPU TCP (L1 Data Cache)")
     p_popMandatoryQueue;
   }
 
+  // Transition to be called when a load request with GLC or SLC flag set arrives
+  // at L1. Since the entry is invalid, there isn't anything to forward to L2,
+  // so just issue read.
+  transition(I, LoadBypassEvict) {TagArrayRead, TagArrayWrite} {
+    uu_profileDataMiss;
+    n_issueRdBlk;
+    p_popMandatoryQueue;
+  }
+
   transition({V, I}, Atomic, A) {TagArrayRead, TagArrayWrite} {
     t_allocateTBE;
     mru_updateMRU;