arch-vega: Add missing operand size for ds_write2st64_b64

This instruction takes three operands (address, and two datas) but there
were only operand sizes for two operands tripping assert in default
case.

Change-Id: I3f505b6432aee5f3f265acac46b83c0c7daff3e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67071
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

src/arch/amdgpu/vega/insts/instructions.hh

@@ -33553,7 +33553,9 @@ namespace VegaISA
             switch (opIdx) {
               case 0: //vgpr_a
                 return 4;
-              case 1: //vgpr_d1
+              case 1: //vgpr_d0
+                return 8;
+              case 2: //vgpr_d1
                 return 8;
               default:
                 fatal("op idx %i out of bounds\n", opIdx);