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  • 87e774c1d5 arch-x86,sim-se: Add clone3 syscall Bobby R. Bruce 2022-10-24 11:36:32 -07:00
  • c2541a8175 arch-arm: Use ThreadContext in ArmISA::currEL implementation Giacomo Travaglini 2022-10-21 16:21:41 +01:00
  • 506bd9d9e7 dev-arm: Use ThreadContext instead if ISA in GICV3 cpu interface Giacomo Travaglini 2022-10-21 12:36:56 +01:00
  • 8a78358a30 arch-arm: Allow TarmacTracer to dump trace to a file Giacomo Travaglini 2022-09-28 20:33:45 +01:00
  • 9a9de78811 dev-arm: Implement System Security Control registers Giacomo Travaglini 2022-09-29 14:56:56 +01:00
  • 4db981576e arch-arm: Setup ThreadContext in GICv3 cpu interface Giacomo Travaglini 2022-10-13 15:30:08 +01:00
  • 62ce119139 arch-arm: Always use AArch64 version of HCR/SCR Giacomo Travaglini 2022-10-12 18:51:31 +01:00
  • a13549ebef scons: Capture TMPDIR envvar handsomeliu 2022-10-25 16:46:00 +08:00
  • 32e4ac65a8 tests: Adding trusted stats for stats tests. Mahyar Samani 2022-04-04 13:27:16 -07:00
  • a3d2f68120 tests: Adding tests for gem5stats. Mahyar Samani 2022-01-21 11:46:53 -08:00
  • 84acdd4836 stdlib: add SimPoint checkpoint generator Zhantong Qiu 2022-10-11 16:49:08 -07:00
  • eed80d083e arch-arm: Set ZCR_ELx before updating vector length in decoder Sascha Bischoff 2022-07-08 10:43:35 +01:00
  • c021bb6099 tests: Update presubmit.sh to use Clang-14 Bobby R. Bruce 2022-10-10 11:44:02 -07:00
  • 21cb85f201 tests: Updating the tests to use Ubuntu 22.04 docker image Bobby R. Bruce 2022-10-10 11:35:06 -07:00
  • 042d1433b9 arch-x86: Fix CPUID for most recent GLIBC Jason Lowe-Power 2022-10-19 11:31:20 -07:00
  • ebc2ad4165 arch-x86: Ignore Linux X86-64 syscall 334 "rseq" Bobby R. Bruce 2022-10-17 17:03:26 -07:00
  • ed89490222 arch-x86: Expand Linux X86-64 Syscalls up to number 334 Bobby R. Bruce 2022-10-17 16:37:35 -07:00
  • 1bb68ff893 stdlib,mem-ruby: Add DVM TBEs to CHI in stdlib Jason Lowe-Power 2022-10-17 17:08:45 -07:00
  • a68e842332 mem-ruby: Fix replacement policy in MESI_Two_Level Jarvis Jia 2022-10-11 22:19:21 -05:00
  • 6840c5e7ea tests: Fix verifier '_iterable_regex' func for None regex Bobby R. Bruce 2022-10-19 12:48:25 -07:00
  • dd4f3d1fa4 configs: Add example memory traffic runscript Jason Lowe-Power 2022-09-30 18:04:14 -07:00
  • b3372a7053 stdlib: Update TestBoard to work with Simulator Jason Lowe-Power 2022-09-30 17:47:52 -07:00
  • b8e6e3aa43 python: Update -c to work like normal python Jason Lowe-Power 2022-09-02 12:02:33 -07:00
  • 32e7ce3f19 fastmodel: improve debug message for resource not found Yu-hsin Wang 2022-10-17 13:07:11 +08:00
  • ca31ce92a1 scons: fix systrace header test Yu-hsin Wang 2022-10-17 13:59:18 +08:00
  • bc914c949f sim,sim-se: Fixes the bug of missing "/" in path resolution Jason Yu 2022-10-13 15:53:14 +08:00
  • 2472b27c8f tests: Move 'riscvmatched-fs.py' example test to weekly Bobby R. Bruce 2022-10-17 10:49:32 -07:00
  • 221dc014db arch-arm: Use scoped enum for ExceptionClass Giacomo Travaglini 2022-10-12 17:50:05 +01:00
  • a4dcd58569 arch-arm: Fix QDADD/QDSUB implementation Giacomo Travaglini 2022-10-14 11:51:06 +01:00
  • 21020aa778 systemc: prevent from invalidate callback re-registration Yu-hsin Wang 2022-10-13 17:05:39 +08:00
  • 9e76e7a321 scons: fix protobuf action for imports Adrián Herrera Arcila 2022-10-06 16:02:17 +00:00
  • 039e9438c1 arch-arm: Fix linking error in aapcs64 unittests Giacomo Travaglini 2022-10-14 10:24:21 +01:00
  • 07f4dd19ad util-docker: Create ALL/gem5.fast docker image with min-deps Bobby R. Bruce 2022-10-12 12:33:06 -07:00
  • e501078787 sim-se,arch-riscv: Fixes file-related flags for riscv64 target Jason Yu 2022-10-13 16:45:40 +08:00
  • a648be2338 dev-amdgpu: Add an SDMA data debug flag Matthew Poremba 2022-10-12 14:51:02 -07:00
  • e48285c244 arch-vega: Implement PDE2 and PDE1 as PTE Matthew Poremba 2022-10-12 14:48:49 -07:00
  • a713d333e0 sysetmc: add missing NO_ACCESS flags in get_direct_mem_ptr Yu-hsin Wang 2022-10-12 17:11:48 +08:00
  • 958b7f8ee8 sysetmc: fix the leak in TlmToGem5Bridge Yu-hsin Wang 2022-10-12 17:06:59 +08:00
  • 9bac517337 tests: Run ALL unit-tests with the nightly script Giacomo Travaglini 2022-10-11 10:27:44 +01:00
  • 9617e12079 misc: Suggest usage of ALL instead of NULL in TESTING.md Giacomo Travaglini 2022-10-11 10:22:36 +01:00
  • ee53d38bae tests: Add 'riscvmatched-fs.py' example to long/nightly tests Bobby R. Bruce 2022-10-05 11:44:29 -07:00
  • 9ac075ea36 stdlib: added errout and output file option in SE process Zhantong Qiu 2022-10-05 14:11:21 -07:00
  • 0ac27fd0bc util-docker,tests: Update supported/test OS to Ubuntu 22.04 Bobby R. Bruce 2022-10-04 17:21:08 -07:00
  • 555ed60eaa util-docker,tests: Add Clang-14 compiler image and test Bobby R. Bruce 2022-10-04 16:45:41 -07:00
  • 57a5bebe80 util-docker,tests: Add Clang-13 compiler image and test Bobby R. Bruce 2022-10-04 16:40:34 -07:00
  • be64af890a util-docker,tests: Add GCC-12 compiler image and test Bobby R. Bruce 2022-10-04 16:31:33 -07:00
  • 8c34a8bf92 util-docker: Add 'ubuntu-22.04_gcc-version' Bobby R. Bruce 2022-10-04 16:23:34 -07:00
  • 6e182b025d mem-ruby: Fix clang-14 compilation warning "use of bitwise" Bobby R. Bruce 2022-10-05 11:04:44 -07:00
  • abad2d6532 mem: Fix 'unused variable' warnings Bobby R. Bruce 2022-10-05 13:54:03 -07:00
  • d2a6d2f7ee stdlib: Add _post_instantiate function Jason Lowe-Power 2022-09-30 17:39:54 -07:00
  • 55f80ae0a1 stdlib: Allow cache_hierarchy to be optional Jason Lowe-Power 2022-09-30 17:26:25 -07:00
  • 007a99e9a0 stdlib: Update the default exit events and warning Jason Lowe-Power 2022-10-07 11:56:04 -07:00
  • 0e20edac34 systemc: fix flexible conversion when reusing transactions Yu-hsin Wang 2022-09-27 12:53:10 +08:00
  • ec696c00b2 gpu-compute: Add missing initial reg state in WF Matthew Poremba 2022-10-06 09:43:04 -07:00
  • e844f17045 tests: Exclude ARM KVM tests from nightly run Bobby R. Bruce 2022-10-04 16:00:53 -07:00
  • 925b1b5c8e arch-vega: Implement V_XAD_U32 instruction Matthew Poremba 2022-10-01 09:32:29 -07:00
  • e94c9f362c base: singleStep can't be interupted by trap from other thread. Quentin Forcioli 2022-08-18 12:07:22 +02:00
  • bff69e4792 base: adding a scheduleTrapEvent Quentin Forcioli 2022-08-30 17:18:48 +02:00
  • 2ae9692dfe base, sim: Adding support for message to GDB from python Quentin Forcioli 2022-08-12 15:44:54 +02:00
  • eeaeee15aa base: adding queryAttached and querySymbol to GDB Quentin Forcioli 2022-08-12 15:44:54 +02:00
  • 3e43603dcc base: adding support for O packet Quentin Forcioli 2022-08-12 15:44:54 +02:00
  • bb78d14c08 base: Adding stop reason and T Packet to the GDB stub Quentin Forcioli 2022-08-12 15:44:54 +02:00
  • cee2aa39b6 base: cmdIsThreadAlive implementation Quentin Forcioli 2022-08-12 15:44:54 +02:00
  • e6287f7b19 base: making GDB's getbyte and send more resilient Quentin Forcioli 2022-08-12 15:44:54 +02:00
  • 832b0ee6b9 base: Adding multi-letter command support to GDB stub Quentin Forcioli 2022-08-12 15:44:54 +02:00
  • 335d2e187e arch-x86, mem: Add support to tag tlb entries with PCID Ayaz Akram 2020-10-08 18:32:42 -07:00
  • 09aeb51350 arch-x86, mem: Add support for PCID to x86 Ayaz Akram 2020-10-08 18:13:25 -07:00
  • ea26611a01 arch-x86: Assign thread context id to APIC id Ayaz Akram 2020-10-08 19:01:28 -07:00
  • f59eb93660 tests: Add 'checkpoint-path' to simpoints stdlib example Bobby R. Bruce 2022-10-03 13:11:43 -07:00
  • 64a087e5e8 tests: Add 'checkpoint-path' to checkpoint stdlib example Bobby R. Bruce 2022-10-03 12:41:25 -07:00
  • 3e51091806 tests: Add Simpoints example scripts as tests Bobby R. Bruce 2022-09-28 17:27:23 -07:00
  • cc3c15f1e0 configs, tests: Use proper releases in KVM simulations Giacomo Travaglini 2022-09-26 15:01:27 +01:00
  • 597a2ce4c1 arch-arm: Add ArmRelease factory function to be used in KVM mode Giacomo Travaglini 2022-09-26 14:39:08 +01:00
  • 317bfd62bd dev: fix device number check error in IDE controller Earl Ou 2022-10-02 19:16:49 -07:00
  • 4f09acb2f5 arch-arm: Add the remove method to the ArmRelease class Giacomo Travaglini 2022-09-26 14:37:40 +01:00
  • da5a4d3d8a stdlib, configs: Add example FS script for RISCV Matched paikunal 2022-09-30 14:51:16 -07:00
  • 7c0ab07ee2 dev-arm: Fix GICv3 GICD_ITARGETSR address range Giacomo Travaglini 2022-10-03 09:48:34 +01:00
  • 336e732d54 misc: Replace namespace Trace with lowercase trace Giacomo Travaglini 2022-09-28 16:01:17 +01:00
  • 2f1d67f8fe dev-amdgpu: Remove cached copy of device memory Matthew Poremba 2022-09-29 07:50:16 -07:00
  • a3842f877a configs, gpu-compute: Add configurable L1 access latencies vramadas95 2022-09-29 13:39:30 -05:00
  • 4662e18981 stdlib: Edit RiscvMatched RTC paikunal 2022-09-30 14:37:11 -07:00
  • 9a1074d27f scons: Fix variable not found error Jason Lowe-Power 2022-09-30 14:11:28 -07:00
  • e7a73c7b59 tests: Fix error in Arm test Jason Lowe-Power 2022-09-29 14:35:39 -07:00
  • a57f08f355 mem-garnet: Add masked functionalRead support Carlos Falquez 2021-06-15 12:40:12 +02:00
  • 14312b650a configs: fix CHI config for Garnet Tiago Mück 2022-09-22 14:02:36 -05:00
  • ae266b3a85 configs: fix CustomMesh router parent Tiago Mück 2021-06-21 07:56:46 -05:00
  • 027b508a38 mem-ruby: fix missing transition in CHI-mem Tiago Mück 2022-05-24 16:48:22 -05:00
  • c6a460eff4 mem-ruby: fix CHI memory controller Tiago Mück 2022-05-24 15:27:16 -05:00
  • 3871f57dc3 configs: set requestToMemory buffer size for CHI Tiago Mück 2022-05-16 17:46:33 -05:00
  • 06a8a47322 configs: fix CHI mem buffers Tiago Mück 2021-06-17 15:06:43 -05:00
  • ba3aa067a3 configs: CHI inc transitions_per_cycle Tiago Mück 2021-04-13 20:16:34 -05:00
  • eb5eab360f configs,gpu-compute: Add configurable LDS bus latency vramadas95 2022-09-14 15:35:53 -05:00
  • c1de2b8762 tests: Move the arm+ruby tests to not use ALL Jason Lowe-Power 2022-09-26 09:49:28 -07:00
  • 1dfd39499f mem-ruby: fix downstream destinations Tiago Mück 2021-07-19 19:39:39 -05:00
  • 9f550d5519 systemc: Fix -Wunused-variable with structured binding Giacomo Travaglini 2022-09-26 17:35:19 +01:00
  • a12ac1a877 tests: Fix errors in arm switcheroo Jason Lowe-Power 2022-09-26 09:48:03 -07:00
  • d000ccf738 fastmodel: correct the control signal for AmbaFromTlmBridge Yu-hsin Wang 2022-09-22 11:57:23 +08:00
  • 344e2ae823 systemc: associate tlm payload and gem5 packet in blocking interfaces Yu-hsin Wang 2022-09-22 11:56:39 +08:00
  • 5d35e22518 systemc: gem5_to_tlm bridge should reuse existed tlm payload Yu-hsin Wang 2022-09-22 10:51:21 +08:00
  • f17c056760 util: added workbegin and workend in m5 util Zhantong Qiu 2022-09-21 15:06:50 -07:00