arch-arm: Setup ThreadContext in GICv3 cpu interface

Change-Id: If019b4b114031f880dff43e05658a162c201ea6a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64912
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/dev/arm/gic_v3_cpu_interface.cc

@@ -81,8 +81,9 @@ Gicv3CPUInterface::resetHppi(uint32_t intid)
 }
 
 void
-Gicv3CPUInterface::setThreadContext(ThreadContext *tc)
+Gicv3CPUInterface::setThreadContext(ThreadContext *_tc)
 {
+    tc = _tc;
     maintenanceInterrupt = gic->params().maint_int->get(tc);
     fatal_if(maintenanceInterrupt->num() >= redistributor->irqPending.size(),
         "Invalid maintenance interrupt number\n");

src/dev/arm/gic_v3_cpu_interface.hh

@@ -71,6 +71,7 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
     uint32_t cpuId;
 
     ArmInterruptPin *maintenanceInterrupt;
+    ThreadContext *tc;
 
     BitUnion64(ICC_CTLR_EL1)
         Bitfield<63, 20> res0_3;