diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc
index b089ba0bda..40ca1ccd3a 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -81,8 +81,9 @@ Gicv3CPUInterface::resetHppi(uint32_t intid)
 }
 
 void
-Gicv3CPUInterface::setThreadContext(ThreadContext *tc)
+Gicv3CPUInterface::setThreadContext(ThreadContext *_tc)
 {
+    tc = _tc;
     maintenanceInterrupt = gic->params().maint_int->get(tc);
     fatal_if(maintenanceInterrupt->num() >= redistributor->irqPending.size(),
         "Invalid maintenance interrupt number\n");
diff --git a/src/dev/arm/gic_v3_cpu_interface.hh b/src/dev/arm/gic_v3_cpu_interface.hh
index dfc17afb38..e860373fb5 100644
--- a/src/dev/arm/gic_v3_cpu_interface.hh
+++ b/src/dev/arm/gic_v3_cpu_interface.hh
@@ -71,6 +71,7 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
     uint32_t cpuId;
 
     ArmInterruptPin *maintenanceInterrupt;
+    ThreadContext *tc;
 
     BitUnion64(ICC_CTLR_EL1)
         Bitfield<63, 20> res0_3;