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fastmodel: improve debug message for resource not found

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The conversion logic between gem5 register id and iris resouce id is
duplicated in read and write function. Some of them also doesn't handle
the invalid id correctly. This change wraps the logic, fixes them, and
improves the debug messages by printing the register names.

Change-Id: I093d05f5f06d804d5f01988c2a7ffa60244c5516
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64651
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
This commit is contained in:
Yu-hsin Wang
2022-10-17 13:07:11 +08:00
parent ca31ce92a1
commit 32e7ce3f19
2 changed files with 96 additions and 34 deletions
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124
src/arch/arm/fastmodel/iris/thread_context.cc
View File

@@ -604,11 +604,24 @@ ThreadContext::pcState(const PCStateBase &val)
call().resource_write(_instId, result, pcRscId, pc);
}
iris::ResourceId
ThreadContext::getMiscRegRscId(RegIndex misc_reg) const
{
iris::ResourceId rsc_id = iris::IRIS_UINT64_MAX;
if (misc_reg < miscRegIds.size())
rsc_id = miscRegIds.at(misc_reg);
panic_if(rsc_id == iris::IRIS_UINT64_MAX,
"Misc reg %s is not supported by fast model.",
ArmISA::miscRegClass[misc_reg]);
return rsc_id;
}
RegVal
ThreadContext::readMiscRegNoEffect(RegIndex misc_reg) const
{
iris::ResourceReadResult result;
call().resource_read(_instId, result, miscRegIds.at(misc_reg));
call().resource_read(_instId, result, getMiscRegRscId(misc_reg));
return result.data.at(0);
}
@@ -616,7 +629,7 @@ void
ThreadContext::setMiscRegNoEffect(RegIndex misc_reg, const RegVal val)
{
iris::ResourceWriteResult result;
call().resource_write(_instId, result, miscRegIds.at(misc_reg), val);
call().resource_write(_instId, result, getMiscRegRscId(misc_reg), val);
}
RegVal
@@ -766,29 +779,43 @@ ThreadContext::getWritableReg(const RegId &reg)
}
}
iris::ResourceId
ThreadContext::getIntRegRscId(RegIndex int_reg) const
{
ArmISA::CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
auto &regIds = cpsr.width ? intReg32Ids : intReg64Ids;
iris::ResourceId rsc_id = iris::IRIS_UINT64_MAX;
if (int_reg < regIds.size())
rsc_id = regIds.at(int_reg);
panic_if(rsc_id == iris::IRIS_UINT64_MAX,
"Int reg %s is not supported by fast model.",
ArmISA::intRegClass[int_reg]);
return rsc_id;
}
RegVal
ThreadContext::readIntReg(RegIndex reg_idx) const
{
ArmISA::CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
iris::ResourceReadResult result;
if (cpsr.width)
call().resource_read(_instId, result, intReg32Ids.at(reg_idx));
else
call().resource_read(_instId, result, intReg64Ids.at(reg_idx));
call().resource_read(_instId, result, getIntRegRscId(reg_idx));
return result.data.at(0);
}
void
ThreadContext::setIntReg(RegIndex reg_idx, RegVal val)
{
ArmISA::CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
iris::ResourceWriteResult result;
if (cpsr.width)
call().resource_write(_instId, result, intReg32Ids.at(reg_idx), val);
else
call().resource_write(_instId, result, intReg64Ids.at(reg_idx), val);
call().resource_write(_instId, result, getIntRegRscId(reg_idx), val);
}
iris::ResourceId
ThreadContext::getIntRegFlatRscId(RegIndex int_reg) const
{
iris::ResourceId rsc_id = iris::IRIS_UINT64_MAX;
if (int_reg < flattenedIntIds.size())
rsc_id = flattenedIntIds.at(int_reg);
return rsc_id;
}
/*
@@ -798,45 +825,63 @@ ThreadContext::setIntReg(RegIndex reg_idx, RegVal val)
RegVal
ThreadContext::readIntRegFlat(RegIndex idx) const
{
if (idx >= flattenedIntIds.size())
return 0;
iris::ResourceId res_id = flattenedIntIds.at(idx);
if (res_id == iris::IRIS_UINT64_MAX)
auto rsc_id = getIntRegFlatRscId(idx);
if (rsc_id == iris::IRIS_UINT64_MAX)
return 0;
iris::ResourceReadResult result;
call().resource_read(_instId, result, res_id);
call().resource_read(_instId, result, rsc_id);
return result.data.at(0);
}
void
ThreadContext::setIntRegFlat(RegIndex idx, uint64_t val)
{
iris::ResourceId res_id =
(idx >= flattenedIntIds.size()) ? iris::IRIS_UINT64_MAX :
flattenedIntIds.at(idx);
panic_if(res_id == iris::IRIS_UINT64_MAX,
"Int reg %d is not supported by fast model.", idx);
auto rsc_id = getIntRegFlatRscId(idx);
panic_if(rsc_id == iris::IRIS_UINT64_MAX,
"Int reg %s is not supported by fast model.",
ArmISA::intRegClass[idx]);
iris::ResourceWriteResult result;
call().resource_write(_instId, result, flattenedIntIds.at(idx), val);
call().resource_write(_instId, result, rsc_id, val);
}
iris::ResourceId
ThreadContext::getCCRegFlatRscId(RegIndex cc_reg) const
{
iris::ResourceId rsc_id = iris::IRIS_UINT64_MAX;
if (cc_reg < ccRegIds.size())
rsc_id = ccRegIds.at(cc_reg);
return rsc_id;
}
RegVal
ThreadContext::readCCRegFlat(RegIndex idx) const
{
if (idx >= ccRegIds.size())
auto rsc_id = getCCRegFlatRscId(idx);
if (rsc_id == iris::IRIS_UINT64_MAX)
return 0;
iris::ResourceReadResult result;
call().resource_read(_instId, result, ccRegIds.at(idx));
call().resource_read(_instId, result, rsc_id);
return result.data.at(0);
}
void
ThreadContext::setCCRegFlat(RegIndex idx, RegVal val)
{
panic_if(idx >= ccRegIds.size(),
"CC reg %d is not supported by fast model.", idx);
auto rsc_id = getCCRegFlatRscId(idx);
panic_if(rsc_id == iris::IRIS_UINT64_MAX,
"CC reg %s is not supported by fast model.",
ArmISA::ccRegClass[idx]);
iris::ResourceWriteResult result;
call().resource_write(_instId, result, ccRegIds.at(idx), val);
call().resource_write(_instId, result, rsc_id, val);
}
iris::ResourceId
ThreadContext::getVecRegRscId(RegIndex vec_reg) const
{
iris::ResourceId rsc_id = iris::IRIS_UINT64_MAX;
if (vec_reg < vecRegIds.size())
rsc_id = vecRegIds.at(vec_reg);
return rsc_id;
}
const ArmISA::VecRegContainer &
@@ -849,11 +894,12 @@ ThreadContext::readVecReg(const RegId &reg_id) const
// Ignore accesses to registers which aren't architected. gem5 defines a
// few extra registers which it uses internally in the implementation of
// some instructions.
if (idx >= vecRegIds.size())
auto rsc_id = getVecRegRscId(reg_id);
if (rsc_id == iris::IRIS_UINT64_MAX)
return reg;
iris::ResourceReadResult result;
call().resource_read(_instId, result, vecRegIds.at(idx));
call().resource_read(_instId, result, rsc_id);
size_t data_size = result.data.size() * (sizeof(*result.data.data()));
size_t size = std::min(data_size, reg.size());
memcpy(reg.as<uint8_t>(), (void *)result.data.data(), size);
@@ -867,6 +913,15 @@ ThreadContext::readVecRegFlat(RegIndex idx) const
return readVecReg(ArmISA::vecRegClass[idx]);
}
iris::ResourceId
ThreadContext::getVecPredRegRscId(RegIndex vec_reg) const
{
iris::ResourceId rsc_id = iris::IRIS_UINT64_MAX;
if (vec_reg < vecPredRegIds.size())
rsc_id = vecPredRegIds.at(vec_reg);
return rsc_id;
}
const ArmISA::VecPredRegContainer &
ThreadContext::readVecPredReg(const RegId &reg_id) const
{
@@ -875,11 +930,12 @@ ThreadContext::readVecPredReg(const RegId &reg_id) const
ArmISA::VecPredRegContainer &reg = vecPredRegs.at(idx);
reg.reset();
if (idx >= vecPredRegIds.size())
auto rsc_id = getVecPredRegRscId(reg_id);
if (rsc_id == iris::IRIS_UINT64_MAX)
return reg;
iris::ResourceReadResult result;
call().resource_read(_instId, result, vecPredRegIds.at(idx));
call().resource_read(_instId, result, rsc_id);
size_t offset = 0;
size_t num_bits = reg.NUM_BITS;

6
src/arch/arm/fastmodel/iris/thread_context.hh
View File

@@ -286,8 +286,10 @@ class ThreadContext : public gem5::ThreadContext
void setReg(const RegId &reg, RegVal val) override;
void setReg(const RegId &reg, const void *val) override;
iris::ResourceId getIntRegRscId(RegIndex int_reg) const;
virtual RegVal readIntReg(RegIndex reg_idx) const;
iris::ResourceId getVecRegRscId(RegIndex vec_reg) const;
virtual const ArmISA::VecRegContainer &readVecReg(const RegId &reg) const;
virtual ArmISA::VecRegContainer &
getWritableVecReg(const RegId &reg)
@@ -301,6 +303,7 @@ class ThreadContext : public gem5::ThreadContext
panic("%s not implemented.", __FUNCTION__);
}
iris::ResourceId getVecPredRegRscId(RegIndex vec_reg) const;
virtual const ArmISA::VecPredRegContainer &
readVecPredReg(const RegId &reg) const;
virtual ArmISA::VecPredRegContainer &
@@ -347,6 +350,7 @@ class ThreadContext : public gem5::ThreadContext
const PCStateBase &pcState() const override;
void pcState(const PCStateBase &val) override;
iris::ResourceId getMiscRegRscId(RegIndex misc_reg) const;
RegVal readMiscRegNoEffect(RegIndex misc_reg) const override;
RegVal
readMiscReg(RegIndex misc_reg) override
@@ -387,6 +391,7 @@ class ThreadContext : public gem5::ThreadContext
* serialization code to access all registers.
*/
iris::ResourceId getIntRegFlatRscId(RegIndex int_reg) const;
virtual RegVal readIntRegFlat(RegIndex idx) const;
virtual void setIntRegFlat(RegIndex idx, uint64_t val);
@@ -426,6 +431,7 @@ class ThreadContext : public gem5::ThreadContext
panic("%s not implemented.", __FUNCTION__);
}
iris::ResourceId getCCRegFlatRscId(RegIndex cc_reg) const;
virtual RegVal readCCRegFlat(RegIndex idx) const;
virtual void setCCRegFlat(RegIndex idx, RegVal val);
/** @} */