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mem-ruby: fix CHI memory controller

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Break up the transition to READING_MEM into two separate steps so
contention at the requestToMemory queue won't block the TBE
initialization.

JIRA: https://gem5.atlassian.net/browse/GEM5-1195

Change-Id: Ifa0ee589bde67eb30e7c0b315ff41f22b61e8db7
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63675
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Tiago Mück
2022-05-24 15:27:16 -05:00
committed by Tiago Muck
parent 3871f57dc3
commit c6a460eff4
1 changed files with 17 additions and 3 deletions
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20
src/mem/ruby/protocol/chi/CHI-mem.sm
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021 ARM Limited
* Copyright (c) 2021,2022 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -119,6 +119,7 @@ machine(MachineType:Memory, "Memory controller interface") :
Trigger_ReceiveDone, desc="";
Trigger_SendRetry, desc="";
Trigger_SendPCrdGrant, desc="";
Trigger_SendMemoryRead, desc="";
}
@@ -551,6 +552,14 @@ machine(MachineType:Memory, "Memory controller interface") :
}
}
action(triggerSendMemoryRead, "tsmr", desc="Trigger sendMemoryRead") {
assert(is_valid(tbe));
enqueue(triggerOutPort, TriggerMsg, 0) {
out_msg.addr := address;
out_msg.event := Event:Trigger_SendMemoryRead;
}
}
action(sendMemoryRead, "smr", desc="Send request to memory") {
assert(is_valid(tbe));
enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) {
@@ -698,18 +707,23 @@ machine(MachineType:Memory, "Memory controller interface") :
transition(READY, ReadNoSnp, READING_MEM) {
allocateTBE;
initializeFromReqTBE;
sendMemoryRead;
triggerSendMemoryRead;
popReqInQueue;
}
transition(READY, ReadNoSnpSep, READING_MEM) {
allocateTBE;
initializeFromReqTBE;
sendMemoryRead;
triggerSendMemoryRead;
sendReadReceipt;
popReqInQueue;
}
transition(READING_MEM, Trigger_SendMemoryRead) {
sendMemoryRead;
popTriggerQueue;
}
transition(READING_MEM, MemoryData, SENDING_NET_DATA) {
prepareSend;
sendDataAndCheck;