derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

dev-arm: Use ThreadContext instead if ISA in GICV3 cpu interface

Browse Source 
Some CPU wrappers like the Fastmodel one do extend the
ThreadContext interface in order to retrieve system register
state... By bypassing the TC interface and by using the ISA
instead, we are basically forcing users to extend the ISA
as well to intercept these calls.

So with this patch we are making sure every system register is accessed
(like HCR_EL2 or SCR_EL3) through the thread context. This of course
does not apply to the CPU interface registers as we still use the ISA
storage for them.  In the future we should probably move that storage
from the ISA class to the Gicv3CPUInterface class itself

This is also simplifying Gicv3CPUInterface::isEL3OrMon:
currEL already covers the AArch32 case so no need to
differentiate between AArch32 and AArch64

Change-Id: I446a14a6e12b77e1a62040b3422f79ae52cc9eec
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64913
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2022-10-21 12:36:56 +01:00
parent 8a78358a30
commit 506bd9d9e7
1 changed files with 11 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

35
src/dev/arm/gic_v3_cpu_interface.cc
View File

@@ -92,7 +92,7 @@ Gicv3CPUInterface::setThreadContext(ThreadContext *_tc)
bool
Gicv3CPUInterface::getHCREL2FMO() const
{
HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
if (hcr.tge && hcr.e2h) {
return false;
@@ -106,7 +106,7 @@ Gicv3CPUInterface::getHCREL2FMO() const
bool
Gicv3CPUInterface::getHCREL2IMO() const
{
HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
if (hcr.tge && hcr.e2h) {
return false;
@@ -231,7 +231,7 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
uint8_t rprio = highestActivePriority();
if (haveEL(EL3) && !inSecureState() &&
(isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
(tc->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
// Spec section 4.8.1
// For Non-secure access to ICC_RPR_EL1 when SCR_EL3.FIQ == 1
if ((rprio & 0x80) == 0) {
@@ -367,7 +367,7 @@ Gicv3CPUInterface::readMiscReg(int misc_reg)
}
if (haveEL(EL3) && !inSecureState() &&
(isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
(tc->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
// Spec section 4.8.1
// For Non-secure access to ICC_PMR_EL1 when SCR_EL3.FIQ == 1:
if ((value & 0x80) == 0) {
@@ -969,7 +969,7 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
bool irq_is_grp0 = group == Gicv3::G0S;
bool single_sec_state = distributor->DS;
bool irq_is_secure = !single_sec_state && (group != Gicv3::G1NS);
SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
SCR scr_el3 = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
bool route_fiq_to_el3 = scr_el3.fiq;
bool route_irq_to_el3 = scr_el3.irq;
bool route_fiq_to_el2 = hcr_fmo;
@@ -1291,7 +1291,7 @@ Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
}
val &= 0xff;
SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
SCR scr_el3 = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) {
// Spec section 4.8.1
@@ -2340,13 +2340,13 @@ Gicv3CPUInterface::groupEnabled(Gicv3::GroupId group) const
bool
Gicv3CPUInterface::inSecureState() const
{
return isa->inSecureState();
return ArmISA::isSecure(tc);
}
ExceptionLevel
Gicv3CPUInterface::currEL() const
{
return isa->currEL();
return ArmISA::currEL(tc);
}
bool
@@ -2372,32 +2372,19 @@ Gicv3CPUInterface::haveEL(ExceptionLevel el) const
bool
Gicv3CPUInterface::isSecureBelowEL3() const
{
SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
return haveEL(EL3) && scr.ns == 0;
return ArmISA::isSecureBelowEL3(tc);
}
bool
Gicv3CPUInterface::isAA64() const
{
CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
return opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
return ArmISA::inAArch64(tc);
}
bool
Gicv3CPUInterface::isEL3OrMon() const
{
if (haveEL(EL3)) {
CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
if (is_64 && (cpsr.el == EL3)) {
return true;
} else if (!is_64 && (cpsr.mode == MODE_MON)) {
return true;
}
}
return false;
return currEL() == EL3;
}
// Computes ICH_EISR_EL2