configs: fix CHI mem buffers

Disabling randomization for the memory request and response buffers.
CHI requires that memory responses for the same address arrive in
the same order the request was sent.

Change-Id: Ia4236188679beaf2969978675414a870ccd9f94a
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63673
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Tiago Mück
2021-06-17 15:06:43 -05:00
committed by Tiago Muck
parent ba3aa067a3
commit 06a8a47322
2 changed files with 24 additions and 4 deletions

View File

@@ -183,6 +183,16 @@ class OrderedTriggerMessageBuffer(TriggerMessageBuffer):
ordered = True
class MemCtrlMessageBuffer(MessageBuffer):
"""
MessageBuffer exchanging messages with the memory
These buffers should also not be affected by the Ruby tester randomization.
"""
randomization = "disabled"
ordered = True
class CHI_Cache_Controller(Cache_Controller):
"""
Default parameters for a Cache controller
@@ -667,8 +677,8 @@ class CHI_SNF_Base(CHI_Node):
version=Versions.getVersion(Memory_Controller),
ruby_system=ruby_system,
triggerQueue=TriggerMessageBuffer(),
responseFromMemory=MessageBuffer(),
requestToMemory=MessageBuffer(ordered=True),
responseFromMemory=MemCtrlMessageBuffer(),
requestToMemory=MemCtrlMessageBuffer(),
reqRdy=TriggerMessageBuffer(),
transitions_per_cycle=1024,
)

View File

@@ -37,6 +37,16 @@ from m5.objects import (
from .abstract_node import TriggerMessageBuffer
class MemCtrlMessageBuffer(MessageBuffer):
"""
MessageBuffer exchanging messages with the memory
These buffers should also not be affected by the Ruby tester randomization.
"""
randomization = "disabled"
ordered = True
class MemoryController(Memory_Controller):
"""A controller that connects to memory"""
@@ -62,8 +72,8 @@ class MemoryController(Memory_Controller):
def connectQueues(self, network):
self.triggerQueue = TriggerMessageBuffer()
self.responseFromMemory = MessageBuffer()
self.requestToMemory = MessageBuffer(ordered=True)
self.responseFromMemory = MemCtrlMessageBuffer()
self.requestToMemory = MemCtrlMessageBuffer()
self.reqRdy = TriggerMessageBuffer()
self.reqOut = MessageBuffer()