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arch-arm: Fix QDADD/QDSUB implementation

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This got broken by a recent commit [1] which converted a bitwise
OR into the boolean version. While it conceptually made sense
as the saturateOp returns a boolean value, it is not taking
into consideration that saturateOp modifies the first argument
and the boolean version short-circuits the expression preventing
the second expression from being run if the first one is true

Therefore providing an incorrect midRes value.

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/64172

Change-Id: Ibb9b3d37dcccda006006650ef759cdfe385dcfe2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64612
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
This commit is contained in:
Giacomo Travaglini
2022-10-14 11:51:06 +01:00
parent 21020aa778
commit a4dcd58569
1 changed files with 6 additions and 4 deletions
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10
src/arch/arm/isa/insts/data.isa
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@@ -342,8 +342,9 @@ let {{
''', flagType="none", buildCc=False)
buildRegDataInst("qdadd", '''
int32_t midRes;
resTemp = saturateOp<32>(midRes, Op2_sw, Op2_sw) ||
saturateOp<32>(midRes, Op1_sw, midRes);
const bool res0 = saturateOp<32>(midRes, Op2_sw, Op2_sw);
const bool res1 = saturateOp<32>(midRes, Op1_sw, midRes);
resTemp = (res0 || res1) ? 1 : 0;
Dest = midRes;
''', flagType="saturate", buildNonCc=False)
buildRegDataInst("qsub", '''
@@ -377,8 +378,9 @@ let {{
''', flagType="none", buildCc=False)
buildRegDataInst("qdsub", '''
int32_t midRes;
resTemp = saturateOp<32>(midRes, Op2_sw, Op2_sw) ||
saturateOp<32>(midRes, Op1_sw, midRes, true);
const bool res0 = saturateOp<32>(midRes, Op2_sw, Op2_sw);
const bool res1 = saturateOp<32>(midRes, Op1_sw, midRes, true);
resTemp = (res0 || res1) ? 1 : 0;
Dest = midRes;
''', flagType="saturate", buildNonCc=False)
buildRegDataInst("qasx", '''