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arch-vega: Implement ds_write_b8_d16_hi

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Writes a byte to the upper 16-bit input word to an address.

Change-Id: I0bfd573526b9c46585d0008cde07c769b1d29ebd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67411
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Matthew Poremba
2023-01-03 08:08:05 -08:00
parent 89c49d1ab0
commit 905b8ebd22
3 changed files with 97 additions and 2 deletions
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3
src/arch/amdgpu/vega/decoder.cc
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@@ -7706,8 +7706,7 @@ namespace VegaISA
GPUStaticInst*
Decoder::decode_OP_DS__DS_WRITE_B8_D16_HI(MachInst iFmt)
{
fatal("Trying to decode instruction without a class\n");
return nullptr;
return new Inst_DS__DS_WRITE_B8_D16_HI(&iFmt->iFmt_DS);
}
GPUStaticInst*

62
src/arch/amdgpu/vega/insts/instructions.cc
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@@ -34877,6 +34877,68 @@ namespace VegaISA
Inst_DS__DS_WRITE_B8::completeAcc(GPUDynInstPtr gpuDynInst)
{
} // completeAcc
// --- Inst_DS__DS_WRITE_B8_D16_HI class methods ---
Inst_DS__DS_WRITE_B8_D16_HI::Inst_DS__DS_WRITE_B8_D16_HI(InFmt_DS *iFmt)
: Inst_DS(iFmt, "ds_write_b8_d16_hi")
{
setFlag(MemoryRef);
setFlag(Store);
} // Inst_DS__DS_WRITE_B8_D16_HI
Inst_DS__DS_WRITE_B8_D16_HI::~Inst_DS__DS_WRITE_B8_D16_HI()
{
} // ~Inst_DS__DS_WRITE_B8_D16_HI
// --- description from .arch file ---
// MEM[ADDR] = DATA[23:16].
// Byte write in to high word.
void
Inst_DS__DS_WRITE_B8_D16_HI::execute(GPUDynInstPtr gpuDynInst)
{
Wavefront *wf = gpuDynInst->wavefront();
if (gpuDynInst->exec_mask.none()) {
wf->decLGKMInstsIssued();
return;
}
gpuDynInst->execUnitId = wf->execUnitId;
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(
gpuDynInst->computeUnit()->cyclesToTicks(Cycles(24)));
ConstVecOperandU32 addr(gpuDynInst, extData.ADDR);
ConstVecOperandU8 data(gpuDynInst, extData.DATA0);
addr.read();
data.read();
calcAddr(gpuDynInst, addr);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
(reinterpret_cast<VecElemU8*>(gpuDynInst->d_data))[lane]
= bits(data[lane], 23, 16);
}
}
gpuDynInst->computeUnit()->localMemoryPipe.issueRequest(gpuDynInst);
} // execute
void
Inst_DS__DS_WRITE_B8_D16_HI::initiateAcc(GPUDynInstPtr gpuDynInst)
{
Addr offset0 = instData.OFFSET0;
Addr offset1 = instData.OFFSET1;
Addr offset = (offset1 << 8) | offset0;
initMemWrite<VecElemU8>(gpuDynInst, offset);
} // initiateAcc
void
Inst_DS__DS_WRITE_B8_D16_HI::completeAcc(GPUDynInstPtr gpuDynInst)
{
} // completeAcc
// --- Inst_DS__DS_WRITE_B16 class methods ---
Inst_DS__DS_WRITE_B16::Inst_DS__DS_WRITE_B16(InFmt_DS *iFmt)

34
src/arch/amdgpu/vega/insts/instructions.hh
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@@ -31934,6 +31934,40 @@ namespace VegaISA
void completeAcc(GPUDynInstPtr) override;
}; // Inst_DS__DS_WRITE_B8
class Inst_DS__DS_WRITE_B8_D16_HI : public Inst_DS
{
public:
Inst_DS__DS_WRITE_B8_D16_HI(InFmt_DS*);
~Inst_DS__DS_WRITE_B8_D16_HI();
int
getNumOperands() override
{
return numDstRegOperands() + numSrcRegOperands();
} // getNumOperands
int numDstRegOperands() override { return 0; }
int numSrcRegOperands() override { return 2; }
int
getOperandSize(int opIdx) override
{
switch (opIdx) {
case 0: //vgpr_a
return 4;
case 1: //vgpr_d0
return 1;
default:
fatal("op idx %i out of bounds\n", opIdx);
return -1;
}
} // getOperandSize
void execute(GPUDynInstPtr) override;
void initiateAcc(GPUDynInstPtr) override;
void completeAcc(GPUDynInstPtr) override;
}; // Inst_DS__DS_WRITE_B8_D16_HI
class Inst_DS__DS_WRITE_B16 : public Inst_DS
{
public: