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arch-vega: Update API for some flat atomics

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Some recently submitted atomic instructions were using two older APIs.
Update these to use the newer APIs to support all apertures and avoid
compilation issue.

Change-Id: Ibd6bc00177d33236946f54ef8e5c7544af322852
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67977
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
This commit is contained in:
Matthew Poremba
2023-02-15 07:45:57 -08:00
parent 3b4f241fb5
commit f028bd55e0
1 changed files with 6 additions and 15 deletions
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21
src/arch/amdgpu/vega/insts/instructions.cc
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@@ -44984,13 +44984,11 @@ namespace VegaISA
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
ConstVecOperandU32 data(gpuDynInst, extData.DATA);
addr.read();
data.read();
calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET);
calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
@@ -44999,8 +44997,7 @@ namespace VegaISA
}
}
gpuDynInst->computeUnit()->globalMemoryPipe.
issueRequest(gpuDynInst);
issueRequestHelper(gpuDynInst);
} // execute
void
@@ -45091,13 +45088,11 @@ namespace VegaISA
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
ConstVecOperandU32 data(gpuDynInst, extData.DATA);
addr.read();
data.read();
calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET);
calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
@@ -45106,8 +45101,7 @@ namespace VegaISA
}
}
gpuDynInst->computeUnit()->globalMemoryPipe.
issueRequest(gpuDynInst);
issueRequestHelper(gpuDynInst);
} // execute
void
@@ -45226,13 +45220,11 @@ namespace VegaISA
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
ConstVecOperandU32 data(gpuDynInst, extData.DATA);
addr.read();
data.read();
calcAddr(gpuDynInst, addr, extData.SADDR, instData.OFFSET);
calcAddr(gpuDynInst, extData.ADDR, extData.SADDR, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
@@ -45241,8 +45233,7 @@ namespace VegaISA
}
}
gpuDynInst->computeUnit()->globalMemoryPipe.
issueRequest(gpuDynInst);
issueRequestHelper(gpuDynInst);
} // execute
void