arch-riscv: Get rid of redundant reset fault invocation.

It was added in one change, another pending change which also added it
was rebased on top of it, and the redundant addition was left in when
the second change was submitted.

Change-Id: I3faf53bca983d8568af45ec7174c2a064eadc0a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67571
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Roger Chang <rogerycchang@google.com>

src/arch/riscv/bare_metal/fs_workload.cc

@@ -59,11 +59,6 @@ BareMetal::initState()
 {
     Workload::initState();
 
-    for (auto *tc: system->threads) {
-        RiscvISA::Reset().invoke(tc);
-        tc->activate();
-    }
-
     warn_if(!bootloader->buildImage().write(system->physProxy),
             "Could not load sections to memory.");