From de3dba971c0071540ffac24dd1aa5ffa6baa696b Mon Sep 17 00:00:00 2001
From: Gabe Black <gabeblack@google.com>
Date: Thu, 2 Feb 2023 03:26:42 -0800
Subject: [PATCH] arch-riscv: Get rid of redundant reset fault invocation.

It was added in one change, another pending change which also added it
was rebased on top of it, and the redundant addition was left in when
the second change was submitted.

Change-Id: I3faf53bca983d8568af45ec7174c2a064eadc0a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67571
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Roger Chang <rogerycchang@google.com>
---
 src/arch/riscv/bare_metal/fs_workload.cc | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/src/arch/riscv/bare_metal/fs_workload.cc b/src/arch/riscv/bare_metal/fs_workload.cc
index 83f541157a..4f7adb31b6 100644
--- a/src/arch/riscv/bare_metal/fs_workload.cc
+++ b/src/arch/riscv/bare_metal/fs_workload.cc
@@ -59,11 +59,6 @@ BareMetal::initState()
 {
     Workload::initState();
 
-    for (auto *tc: system->threads) {
-        RiscvISA::Reset().invoke(tc);
-        tc->activate();
-    }
-
     warn_if(!bootloader->buildImage().write(system->physProxy),
             "Could not load sections to memory.");