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configs: Start using the new CpuCluster class in example/arm

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Change-Id: I061c6255449dd126cdd1a6935bea510ebe2e8e14
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65892
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
This commit is contained in:
Giacomo Travaglini
2022-10-25 09:31:10 +01:00
parent 8149245ecc
commit 899f702f12
6 changed files with 32 additions and 65 deletions
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2
configs/example/arm/baremetal.py
View File

@@ -122,7 +122,7 @@ def create(args):
# Add CPU clusters to the system
system.cpu_cluster = [
devices.CpuCluster(
devices.ArmCpuCluster(
system, args.num_cores, args.cpu_freq, "1.0V", *cpu_types[args.cpu]
)
]

56
configs/example/arm/devices.py
View File

@@ -1,4 +1,4 @@
# Copyright (c) 2016-2017, 2019, 2021 Arm Limited
# Copyright (c) 2016-2017, 2019, 2021-2022 Arm Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -95,7 +95,7 @@ class MemBus(SystemXBar):
default = Self.badaddr_responder.pio
class CpuCluster(SubSystem):
class ArmCpuCluster(CpuCluster):
def __init__(
self,
system,
@@ -107,7 +107,7 @@ class CpuCluster(SubSystem):
l1d_type,
l2_type,
):
super(CpuCluster, self).__init__()
super().__init__()
self._cpu_type = cpu_type
self._l1i_type = l1i_type
self._l1d_type = l1d_type
@@ -120,24 +120,9 @@ class CpuCluster(SubSystem):
clock=cpu_clock, voltage_domain=self.voltage_domain
)
self.cpus = [
self._cpu_type(
cpu_id=system.numCpus() + idx, clk_domain=self.clk_domain
)
for idx in range(num_cpus)
]
self.generate_cpus(cpu_type, num_cpus)
for cpu in self.cpus:
cpu.createThreads()
cpu.createInterruptController()
cpu.socket_id = system.numCpuClusters()
system.addCpuCluster(self, num_cpus)
def requireCaches(self):
return self._cpu_type.require_caches()
def memoryMode(self):
return self._cpu_type.memory_mode()
system.addCpuCluster(self)
def addL1(self):
for cpu in self.cpus:
@@ -191,7 +176,7 @@ class CpuCluster(SubSystem):
cpu.connectCachedPorts(bus.cpu_side_ports)
class AtomicCluster(CpuCluster):
class AtomicCluster(ArmCpuCluster):
def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
cpu_config = [
ObjectList.cpu_list.get("AtomicSimpleCPU"),
@@ -199,28 +184,24 @@ class AtomicCluster(CpuCluster):
None,
None,
]
super(AtomicCluster, self).__init__(
system, num_cpus, cpu_clock, cpu_voltage, *cpu_config
)
super().__init__(system, num_cpus, cpu_clock, cpu_voltage, *cpu_config)
def addL1(self):
pass
class KvmCluster(CpuCluster):
class KvmCluster(ArmCpuCluster):
def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
cpu_config = [ObjectList.cpu_list.get("ArmV8KvmCPU"), None, None, None]
super(KvmCluster, self).__init__(
system, num_cpus, cpu_clock, cpu_voltage, *cpu_config
)
super().__init__(system, num_cpus, cpu_clock, cpu_voltage, *cpu_config)
def addL1(self):
pass
class FastmodelCluster(SubSystem):
class FastmodelCluster(CpuCluster):
def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
super(FastmodelCluster, self).__init__()
super().__init__()
# Setup GIC
gic = system.realview.gic
@@ -285,12 +266,12 @@ class FastmodelCluster(SubSystem):
self.cpu_hub.a2t = a2t
self.cpu_hub.t2g = t2g
system.addCpuCluster(self, num_cpus)
system.addCpuCluster(self)
def requireCaches(self):
def require_caches(self):
return False
def memoryMode(self):
def memory_mode(self):
return "atomic_noncaching"
def addL1(self):
@@ -330,7 +311,6 @@ class BaseSimpleSystem(ArmSystem):
self.mem_ranges = self.getMemRanges(int(Addr(mem_size)))
self._clusters = []
self._num_cpus = 0
def getMemRanges(self, mem_size):
"""
@@ -357,14 +337,8 @@ class BaseSimpleSystem(ArmSystem):
def numCpuClusters(self):
return len(self._clusters)
def addCpuCluster(self, cpu_cluster, num_cpus):
assert cpu_cluster not in self._clusters
assert num_cpus > 0
def addCpuCluster(self, cpu_cluster):
self._clusters.append(cpu_cluster)
self._num_cpus += num_cpus
def numCpus(self):
return self._num_cpus
def addCaches(self, need_caches, last_cache_level):
if not need_caches:

31
configs/example/arm/fs_bigLITTLE.py
View File

@@ -79,7 +79,7 @@ def _using_pdes(root):
return False
class BigCluster(devices.CpuCluster):
class BigCluster(devices.ArmCpuCluster):
def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
cpu_config = [
ObjectList.cpu_list.get("O3_ARM_v7a_3"),
@@ -87,12 +87,10 @@ class BigCluster(devices.CpuCluster):
devices.L1D,
devices.L2,
]
super(BigCluster, self).__init__(
system, num_cpus, cpu_clock, cpu_voltage, *cpu_config
)
super().__init__(system, num_cpus, cpu_clock, cpu_voltage, *cpu_config)
class LittleCluster(devices.CpuCluster):
class LittleCluster(devices.ArmCpuCluster):
def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
cpu_config = [
ObjectList.cpu_list.get("MinorCPU"),
@@ -100,9 +98,7 @@ class LittleCluster(devices.CpuCluster):
devices.L1D,
devices.L2,
]
super(LittleCluster, self).__init__(
system, num_cpus, cpu_clock, cpu_voltage, *cpu_config
)
super().__init__(system, num_cpus, cpu_clock, cpu_voltage, *cpu_config)
class Ex5BigCluster(devices.CpuCluster):
@@ -113,9 +109,7 @@ class Ex5BigCluster(devices.CpuCluster):
ex5_big.L1D,
ex5_big.L2,
]
super(Ex5BigCluster, self).__init__(
system, num_cpus, cpu_clock, cpu_voltage, *cpu_config
)
super().__init__(system, num_cpus, cpu_clock, cpu_voltage, *cpu_config)
class Ex5LittleCluster(devices.CpuCluster):
@@ -126,9 +120,7 @@ class Ex5LittleCluster(devices.CpuCluster):
ex5_LITTLE.L1D,
ex5_LITTLE.L2,
]
super(Ex5LittleCluster, self).__init__(
system, num_cpus, cpu_clock, cpu_voltage, *cpu_config
)
super().__init__(system, num_cpus, cpu_clock, cpu_voltage, *cpu_config)
def createSystem(
@@ -376,7 +368,7 @@ def build(options):
system.bigCluster = big_model(
system, options.big_cpus, options.big_cpu_clock
)
system.mem_mode = system.bigCluster.memoryMode()
system.mem_mode = system.bigCluster.memory_mode()
all_cpus += system.bigCluster.cpus
# little cluster
@@ -384,23 +376,24 @@ def build(options):
system.littleCluster = little_model(
system, options.little_cpus, options.little_cpu_clock
)
system.mem_mode = system.littleCluster.memoryMode()
system.mem_mode = system.littleCluster.memory_mode()
all_cpus += system.littleCluster.cpus
# Figure out the memory mode
if (
options.big_cpus > 0
and options.little_cpus > 0
and system.bigCluster.memoryMode() != system.littleCluster.memoryMode()
and system.bigCluster.memory_mode()
!= system.littleCluster.memory_mode()
):
m5.util.panic("Memory mode missmatch among CPU clusters")
# create caches
system.addCaches(options.caches, options.last_cache_level)
if not options.caches:
if options.big_cpus > 0 and system.bigCluster.requireCaches():
if options.big_cpus > 0 and system.bigCluster.require_caches():
m5.util.panic("Big CPU model requires caches")
if options.little_cpus > 0 and system.littleCluster.requireCaches():
if options.little_cpus > 0 and system.littleCluster.require_caches():
m5.util.panic("Little CPU model requires caches")
# Create a KVM VM and do KVM-specific configuration

2
configs/example/arm/ruby_fs.py
View File

@@ -115,7 +115,7 @@ def create(args):
# Add CPU clusters to the system
system.cpu_cluster = [
devices.CpuCluster(
devices.ArmCpuCluster(
system,
args.num_cpus,
args.cpu_freq,

2
configs/example/arm/starter_fs.py
View File

@@ -128,7 +128,7 @@ def create(args):
# Add CPU clusters to the system
system.cpu_cluster = [
devices.CpuCluster(
devices.ArmCpuCluster(
system, args.num_cores, args.cpu_freq, "1.0V", *cpu_types[args.cpu]
)
]

4
configs/example/arm/starter_se.py
View File

@@ -102,14 +102,14 @@ class SimpleSeSystem(System):
# Create a cache hierarchy (unless we are simulating a
# functional CPU in atomic memory mode) for the CPU cluster
# and connect it to the shared memory bus.
if self.cpu_cluster.memoryMode() == "timing":
if self.cpu_cluster.memory_mode() == "timing":
self.cpu_cluster.addL1()
self.cpu_cluster.addL2(self.cpu_cluster.clk_domain)
self.cpu_cluster.connectMemSide(self.membus)
# Tell gem5 about the memory mode used by the CPUs we are
# simulating.
self.mem_mode = self.cpu_cluster.memoryMode()
self.mem_mode = self.cpu_cluster.memory_mode()
def numCpuClusters(self):
return len(self._clusters)