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dev-amdgpu: Fix interrupt handler address assignment

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The interrupt handler's base address is sent via MMIO and must be
shifted by 8 bits to convert to a byte address. The current code is
shifting the MMIO dword first then assigning, resulting in the top 8
bits being shifted out.

This changeset fixes the issue by assigning the dword to the 64-bit
address first then shifting after. Similarly, the upper dword is cast to
a 64-bit value first before shifting.

This fixes some "fence fallback timeout" errors in the m5term output.
These timeouts become a problem because the driver will reset after a
few hundred of them, killing any running GPU applications as part of the
process.

Change-Id: I0beec313f533765c94063bcf4de8c65aacf2986b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65092
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
This commit is contained in:
Matthew Poremba
2022-10-30 12:00:04 -07:00
parent 91cd599f05
commit 8899291db6
1 changed files with 3 additions and 4 deletions
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7
src/dev/amdgpu/interrupt_handler.cc
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@@ -202,15 +202,14 @@ AMDGPUInterruptHandler::setCntl(const uint32_t &data)
void
AMDGPUInterruptHandler::setBase(const uint32_t &data)
{
regs.IH_Base = data << 8;
regs.baseAddr |= regs.IH_Base;
regs.baseAddr = data;
regs.baseAddr <<= 8;
}
void
AMDGPUInterruptHandler::setBaseHi(const uint32_t &data)
{
regs.IH_Base_Hi = data;
regs.baseAddr |= ((uint64_t)regs.IH_Base_Hi) << 32;
regs.baseAddr |= static_cast<uint64_t>(data) << 40;
}
void