From 8899291db656dfbb53df8ad4e4e45da1c3b6d797 Mon Sep 17 00:00:00 2001 From: Matthew Poremba Date: Sun, 30 Oct 2022 12:00:04 -0700 Subject: [PATCH] dev-amdgpu: Fix interrupt handler address assignment The interrupt handler's base address is sent via MMIO and must be shifted by 8 bits to convert to a byte address. The current code is shifting the MMIO dword first then assigning, resulting in the top 8 bits being shifted out. This changeset fixes the issue by assigning the dword to the 64-bit address first then shifting after. Similarly, the upper dword is cast to a 64-bit value first before shifting. This fixes some "fence fallback timeout" errors in the m5term output. These timeouts become a problem because the driver will reset after a few hundred of them, killing any running GPU applications as part of the process. Change-Id: I0beec313f533765c94063bcf4de8c65aacf2986b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65092 Tested-by: kokoro Reviewed-by: Matt Sinclair Maintainer: Matt Sinclair --- src/dev/amdgpu/interrupt_handler.cc | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/dev/amdgpu/interrupt_handler.cc b/src/dev/amdgpu/interrupt_handler.cc index 585c1cfc04..a771976d98 100644 --- a/src/dev/amdgpu/interrupt_handler.cc +++ b/src/dev/amdgpu/interrupt_handler.cc @@ -202,15 +202,14 @@ AMDGPUInterruptHandler::setCntl(const uint32_t &data) void AMDGPUInterruptHandler::setBase(const uint32_t &data) { - regs.IH_Base = data << 8; - regs.baseAddr |= regs.IH_Base; + regs.baseAddr = data; + regs.baseAddr <<= 8; } void AMDGPUInterruptHandler::setBaseHi(const uint32_t &data) { - regs.IH_Base_Hi = data; - regs.baseAddr |= ((uint64_t)regs.IH_Base_Hi) << 32; + regs.baseAddr |= static_cast(data) << 40; } void