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arch-arm: Remove ISA::haveGICv3CpuIfc method

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The method is really not needed as we do not implement
GICv3 in legacy mode... Therefore when we want to check if
the GICv3 cpu interface is present, we can just check for
GICv3 being present

Change-Id: I264f887392d188a515480c2e31a4a4da3e67c498
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65173
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2022-10-27 14:00:25 +01:00
parent d348df8763
commit aead8fb0fd
4 changed files with 21 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/arch/arm/isa.cc
View File

@@ -79,8 +79,7 @@ RegClass floatRegClass(FloatRegClass, FloatRegClassName, 0, debug::FloatRegs);
} // anonymous namespace
ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
_decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop),
afterStartup(false)
_decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop)
{
_regClasses.push_back(&flatIntRegClass);
_regClasses.push_back(&floatRegClass);
@@ -513,8 +512,6 @@ ISA::startup()
tc->setHtmCheckpointPtr(std::move(cpt));
}
}
afterStartup = true;
}
void

13
src/arch/arm/isa.hh
View File

@@ -104,8 +104,6 @@ namespace ArmISA
*/
bool impdefAsNop;
bool afterStartup;
SelfDebug * selfDebug;
const MiscRegLUTEntryInitializer
@@ -394,17 +392,6 @@ namespace ArmISA
enums::DecoderFlavor decoderFlavor() const { return _decoderFlavor; }
/** Returns true if the ISA has a GICv3 cpu interface */
bool
haveGICv3CpuIfc() const
{
// gicv3CpuInterface is initialized at startup time, hence
// trying to read its value before the startup stage will lead
// to an error
assert(afterStartup);
return gicv3CpuInterface != nullptr;
}
PARAMS(ArmISA);
ISA(const Params &p);

24
src/arch/arm/regs/misc.cc
View File

@@ -1618,13 +1618,25 @@ faultZcrEL3(const MiscRegLUTEntry &entry,
}
}
Fault
faultGicv3(const MiscRegLUTEntry &entry,
ThreadContext *tc, const MiscRegOp64 &inst)
{
auto gic = static_cast<ArmSystem*>(tc->getSystemPtr())->getGIC();
if (!gic->supportsVersion(BaseGic::GicVersion::GIC_V3)) {
return inst.undefined();
} else {
return NoFault;
}
}
Fault
faultIccSgiEL1(const MiscRegLUTEntry &entry,
ThreadContext *tc, const MiscRegOp64 &inst)
{
auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
if (!isa->haveGICv3CpuIfc())
return inst.undefined();
if (auto fault = faultGicv3(entry, tc, inst); fault != NoFault) {
return fault;
}
const Gicv3CPUInterface::ICH_HCR_EL2 ich_hcr =
tc->readMiscReg(MISCREG_ICH_HCR_EL2);
@@ -1643,9 +1655,9 @@ Fault
faultIccSgiEL2(const MiscRegLUTEntry &entry,
ThreadContext *tc, const MiscRegOp64 &inst)
{
auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
if (!isa->haveGICv3CpuIfc())
return inst.undefined();
if (auto fault = faultGicv3(entry, tc, inst); fault != NoFault) {
return fault;
}
const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
if (ArmSystem::haveEL(tc, EL3) && scr.irq && scr.fiq) {

12
src/arch/arm/utility.cc
View File

@@ -626,19 +626,11 @@ mcrMrc15TrapToHyp(const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss,
break;
// GICv3 regs
case MISCREG_ICC_SGI0R:
{
auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
if (isa->haveGICv3CpuIfc())
trap_to_hyp = hcr.fmo;
}
trap_to_hyp = hcr.fmo;
break;
case MISCREG_ICC_SGI1R:
case MISCREG_ICC_ASGI1R:
{
auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
if (isa->haveGICv3CpuIfc())
trap_to_hyp = hcr.imo;
}
trap_to_hyp = hcr.imo;
break;
case MISCREG_CNTFRQ ... MISCREG_CNTV_TVAL:
// CNTFRQ may be trapped only on reads