arch-arm: Revert 'Setup TC/ISA at construction time..'

Reverts:

dd2f1fb2f8
https://gem5-review.googlesource.com/c/public/gem5/+/65174

and

47bd56ee71
https://gem5-review.googlesource.com/c/public/gem5/+/65291

The 47bd56ee change resulted in the
`SuiteUID:tests/gem5/fs/linux/arm/test.py:realview-switcheroo-noncaching-timing-ALL-x86_64-opt`
nightly test stalling. This behavior can be reproduced with:

```
./build/ALL/gem5.opt tests/gem5/fs/linux/arm/run.py tests/gem5/configs/realview-switcheroo-noncaching-timing.py tests/gem5/resources/arm “$(pwd)”
```

The subsequent change, dd2f1fb2, must be reverted for this change to be
reverted.

Change-Id: I6fed74f33d013f321b93cf1a73eee404cb87ce18
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65732
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65971
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>

src/arch/arm/isa.cc

@@ -523,6 +523,16 @@ ISA::setupThreadContext()
         return;
 
     selfDebug->init(tc);
+
+    Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
+    if (!gicv3)
+        return;
+
+    if (!gicv3CpuInterface)
+        gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
+
+    gicv3CpuInterface->setISA(this);
+    gicv3CpuInterface->setThreadContext(tc);
 }
 
 void
@@ -1998,15 +2008,7 @@ ISA::getGenericTimer()
 BaseISADevice &
 ISA::getGICv3CPUInterface()
 {
-    if (gicv3CpuInterface)
-        return *gicv3CpuInterface.get();
-
-    assert(system);
-    Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
-    panic_if(!gicv3, "The system does not have a GICv3 irq controller\n");
-
-    gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
-
+    panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!");
     return *gicv3CpuInterface.get();
 }
 

src/dev/arm/gic_v3.cc

@@ -147,7 +147,7 @@ Gicv3::init()
 
     for (int i = 0; i < threads; i++) {
         redistributors[i] = new Gicv3Redistributor(this, i);
-        cpuInterfaces[i] = new Gicv3CPUInterface(this, sys->threads[i]);
+        cpuInterfaces[i] = new Gicv3CPUInterface(this, i);
     }
 
     distRange = RangeSize(params().dist_addr,

src/dev/arm/gic_v3_cpu_interface.cc

@@ -55,19 +55,15 @@ using namespace ArmISA;
 const uint8_t Gicv3CPUInterface::GIC_MIN_BPR;
 const uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS;
 
-Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, ThreadContext *_tc)
+Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id)
     : BaseISADevice(),
       gic(gic),
       redistributor(nullptr),
       distributor(nullptr),
-      tc(_tc),
-      maintenanceInterrupt(gic->params().maint_int->get(tc)),
-      cpuId(tc->contextId())
+      cpuId(cpu_id)
 {
     hppi.prio = 0xff;
     hppi.intid = Gicv3::INTID_SPURIOUS;
-
-    setISA(static_cast<ISA*>(tc->getIsaPtr()));
 }
 
 void
@@ -84,6 +80,15 @@ Gicv3CPUInterface::resetHppi(uint32_t intid)
         hppi.prio = 0xff;
 }
 
+void
+Gicv3CPUInterface::setThreadContext(ThreadContext *_tc)
+{
+    tc = _tc;
+    maintenanceInterrupt = gic->params().maint_int->get(tc);
+    fatal_if(maintenanceInterrupt->num() >= redistributor->irqPending.size(),
+        "Invalid maintenance interrupt number\n");
+}
+
 bool
 Gicv3CPUInterface::getHCREL2FMO() const
 {

src/dev/arm/gic_v3_cpu_interface.hh

@@ -68,11 +68,11 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
     Gicv3 * gic;
     Gicv3Redistributor * redistributor;
     Gicv3Distributor * distributor;
-
-    ThreadContext *tc;
-    ArmInterruptPin *maintenanceInterrupt;
     uint32_t cpuId;
 
+    ArmInterruptPin *maintenanceInterrupt;
+    ThreadContext *tc;
+
     BitUnion64(ICC_CTLR_EL1)
         Bitfield<63, 20> res0_3;
         Bitfield<19>     ExtRange;
@@ -359,7 +359,7 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
     void setBankedMiscReg(ArmISA::MiscRegIndex misc_reg, RegVal val) const;
   public:
 
-    Gicv3CPUInterface(Gicv3 * gic, ThreadContext *tc);
+    Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id);
 
     void init();
 
@@ -369,6 +369,7 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
   public: // BaseISADevice
     RegVal readMiscReg(int misc_reg) override;
     void setMiscReg(int misc_reg, RegVal val) override;
+    void setThreadContext(ThreadContext *tc) override;
 };
 
 } // namespace gem5