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dev-arm: Setup TC/ISA at construction time of Gicv3CPUInterface

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We should initialize them as soon as possible to make sure
any Gicv3CPUInterface method uses a valid reference

Change-Id: I8fffebdab9136a9027c4f61bb9413e97031e1969
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65291
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2022-11-04 14:48:31 +00:00
parent a4f86df266
commit 47bd56ee71
4 changed files with 10 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/arch/arm/isa.cc
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@@ -530,9 +530,6 @@ ISA::setupThreadContext()
if (!gicv3CpuInterface)
gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
gicv3CpuInterface->setISA(this);
gicv3CpuInterface->setThreadContext(tc);
}
void

2
src/dev/arm/gic_v3.cc
View File

@@ -147,7 +147,7 @@ Gicv3::init()
for (int i = 0; i < threads; i++) {
redistributors[i] = new Gicv3Redistributor(this, i);
cpuInterfaces[i] = new Gicv3CPUInterface(this, i);
cpuInterfaces[i] = new Gicv3CPUInterface(this, sys->threads[i]);
}
distRange = RangeSize(params().dist_addr,

17
src/dev/arm/gic_v3_cpu_interface.cc
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@@ -55,15 +55,19 @@ using namespace ArmISA;
const uint8_t Gicv3CPUInterface::GIC_MIN_BPR;
const uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS;
Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id)
Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, ThreadContext *_tc)
: BaseISADevice(),
gic(gic),
redistributor(nullptr),
distributor(nullptr),
cpuId(cpu_id)
tc(_tc),
maintenanceInterrupt(gic->params().maint_int->get(tc)),
cpuId(tc->contextId())
{
hppi.prio = 0xff;
hppi.intid = Gicv3::INTID_SPURIOUS;
setISA(static_cast<ISA*>(tc->getIsaPtr()));
}
void
@@ -80,15 +84,6 @@ Gicv3CPUInterface::resetHppi(uint32_t intid)
hppi.prio = 0xff;
}
void
Gicv3CPUInterface::setThreadContext(ThreadContext *_tc)
{
tc = _tc;
maintenanceInterrupt = gic->params().maint_int->get(tc);
fatal_if(maintenanceInterrupt->num() >= redistributor->irqPending.size(),
"Invalid maintenance interrupt number\n");
}
bool
Gicv3CPUInterface::getHCREL2FMO() const
{

7
src/dev/arm/gic_v3_cpu_interface.hh
View File

@@ -68,10 +68,10 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
Gicv3 * gic;
Gicv3Redistributor * redistributor;
Gicv3Distributor * distributor;
uint32_t cpuId;
ArmInterruptPin *maintenanceInterrupt;
ThreadContext *tc;
ArmInterruptPin *maintenanceInterrupt;
uint32_t cpuId;
BitUnion64(ICC_CTLR_EL1)
Bitfield<63, 20> res0_3;
@@ -359,7 +359,7 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
void setBankedMiscReg(ArmISA::MiscRegIndex misc_reg, RegVal val) const;
public:
Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id);
Gicv3CPUInterface(Gicv3 * gic, ThreadContext *tc);
void init();
@@ -369,7 +369,6 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
public: // BaseISADevice
RegVal readMiscReg(int misc_reg) override;
void setMiscReg(int misc_reg, RegVal val) override;
void setThreadContext(ThreadContext *tc) override;
};
} // namespace gem5