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arch-arm: Setup ISA::gicv3CpuInterface on demand only

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This is aligning with what we are already doing with the CoreTimers:
rather than setting up the interface at ISA::startup, we set it
up on the first time the GIC cpu interface is actually required
by the ISA

Change-Id: Iec29b2098ea29ca2886a69c5db8a2bc8d2f6f71e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65174
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2022-10-24 09:49:44 +01:00
parent 47bd56ee71
commit dd2f1fb2f8
1 changed files with 9 additions and 8 deletions
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17
src/arch/arm/isa.cc
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@@ -523,13 +523,6 @@ ISA::setupThreadContext()
return;
selfDebug->init(tc);
Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
if (!gicv3)
return;
if (!gicv3CpuInterface)
gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
}
void
@@ -2005,7 +1998,15 @@ ISA::getGenericTimer()
BaseISADevice &
ISA::getGICv3CPUInterface()
{
panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!");
if (gicv3CpuInterface)
return *gicv3CpuInterface.get();
assert(system);
Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
panic_if(!gicv3, "The system does not have a GICv3 irq controller\n");
gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
return *gicv3CpuInterface.get();
}