From dd2f1fb2f8520849f10fc25fc5eab5beaa90a7d4 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Mon, 24 Oct 2022 09:49:44 +0100 Subject: [PATCH] arch-arm: Setup ISA::gicv3CpuInterface on demand only This is aligning with what we are already doing with the CoreTimers: rather than setting up the interface at ISA::startup, we set it up on the first time the GIC cpu interface is actually required by the ISA Change-Id: Iec29b2098ea29ca2886a69c5db8a2bc8d2f6f71e Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65174 Reviewed-by: Jason Lowe-Power Maintainer: Andreas Sandberg Reviewed-by: Andreas Sandberg Maintainer: Jason Lowe-Power Tested-by: kokoro --- src/arch/arm/isa.cc | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 3aabb5697d..fd19f721b2 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -523,13 +523,6 @@ ISA::setupThreadContext() return; selfDebug->init(tc); - - Gicv3 *gicv3 = dynamic_cast(system->getGIC()); - if (!gicv3) - return; - - if (!gicv3CpuInterface) - gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); } void @@ -2005,7 +1998,15 @@ ISA::getGenericTimer() BaseISADevice & ISA::getGICv3CPUInterface() { - panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!"); + if (gicv3CpuInterface) + return *gicv3CpuInterface.get(); + + assert(system); + Gicv3 *gicv3 = dynamic_cast(system->getGIC()); + panic_if(!gicv3, "The system does not have a GICv3 irq controller\n"); + + gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); + return *gicv3CpuInterface.get(); }