From 9696cb517a6b5be7f3d006c1136853f74123cce5 Mon Sep 17 00:00:00 2001 From: "Bobby R. Bruce" Date: Thu, 17 Nov 2022 15:48:34 -0800 Subject: [PATCH] arch-arm: Revert 'Setup TC/ISA at construction time..' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reverts: dd2f1fb2f8520849f10fc25fc5eab5beaa90a7d4 https://gem5-review.googlesource.com/c/public/gem5/+/65174 and 47bd56ee71ba1d684138365e7123aa779989ba1d https://gem5-review.googlesource.com/c/public/gem5/+/65291 The 47bd56ee change resulted in the `SuiteUID:tests/gem5/fs/linux/arm/test.py:realview-switcheroo-noncaching-timing-ALL-x86_64-opt` nightly test stalling. This behavior can be reproduced with: ``` ./build/ALL/gem5.opt tests/gem5/fs/linux/arm/run.py tests/gem5/configs/realview-switcheroo-noncaching-timing.py tests/gem5/resources/arm “$(pwd)” ``` The subsequent change, dd2f1fb2, must be reverted for this change to be reverted. Change-Id: I6fed74f33d013f321b93cf1a73eee404cb87ce18 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65732 Reviewed-by: Jason Lowe-Power Maintainer: Bobby Bruce Tested-by: kokoro Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65971 Reviewed-by: Bobby Bruce --- src/arch/arm/isa.cc | 20 +++++++++++--------- src/dev/arm/gic_v3.cc | 2 +- src/dev/arm/gic_v3_cpu_interface.cc | 17 +++++++++++------ src/dev/arm/gic_v3_cpu_interface.hh | 9 +++++---- 4 files changed, 28 insertions(+), 20 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index fd19f721b2..a30fd94596 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -523,6 +523,16 @@ ISA::setupThreadContext() return; selfDebug->init(tc); + + Gicv3 *gicv3 = dynamic_cast(system->getGIC()); + if (!gicv3) + return; + + if (!gicv3CpuInterface) + gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); + + gicv3CpuInterface->setISA(this); + gicv3CpuInterface->setThreadContext(tc); } void @@ -1998,15 +2008,7 @@ ISA::getGenericTimer() BaseISADevice & ISA::getGICv3CPUInterface() { - if (gicv3CpuInterface) - return *gicv3CpuInterface.get(); - - assert(system); - Gicv3 *gicv3 = dynamic_cast(system->getGIC()); - panic_if(!gicv3, "The system does not have a GICv3 irq controller\n"); - - gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); - + panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!"); return *gicv3CpuInterface.get(); } diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc index e14d1f2bef..dde3818b07 100644 --- a/src/dev/arm/gic_v3.cc +++ b/src/dev/arm/gic_v3.cc @@ -147,7 +147,7 @@ Gicv3::init() for (int i = 0; i < threads; i++) { redistributors[i] = new Gicv3Redistributor(this, i); - cpuInterfaces[i] = new Gicv3CPUInterface(this, sys->threads[i]); + cpuInterfaces[i] = new Gicv3CPUInterface(this, i); } distRange = RangeSize(params().dist_addr, diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc index a11dd9b8ed..0e1dbaa04b 100644 --- a/src/dev/arm/gic_v3_cpu_interface.cc +++ b/src/dev/arm/gic_v3_cpu_interface.cc @@ -55,19 +55,15 @@ using namespace ArmISA; const uint8_t Gicv3CPUInterface::GIC_MIN_BPR; const uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS; -Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, ThreadContext *_tc) +Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id) : BaseISADevice(), gic(gic), redistributor(nullptr), distributor(nullptr), - tc(_tc), - maintenanceInterrupt(gic->params().maint_int->get(tc)), - cpuId(tc->contextId()) + cpuId(cpu_id) { hppi.prio = 0xff; hppi.intid = Gicv3::INTID_SPURIOUS; - - setISA(static_cast(tc->getIsaPtr())); } void @@ -84,6 +80,15 @@ Gicv3CPUInterface::resetHppi(uint32_t intid) hppi.prio = 0xff; } +void +Gicv3CPUInterface::setThreadContext(ThreadContext *_tc) +{ + tc = _tc; + maintenanceInterrupt = gic->params().maint_int->get(tc); + fatal_if(maintenanceInterrupt->num() >= redistributor->irqPending.size(), + "Invalid maintenance interrupt number\n"); +} + bool Gicv3CPUInterface::getHCREL2FMO() const { diff --git a/src/dev/arm/gic_v3_cpu_interface.hh b/src/dev/arm/gic_v3_cpu_interface.hh index c39fab7647..e860373fb5 100644 --- a/src/dev/arm/gic_v3_cpu_interface.hh +++ b/src/dev/arm/gic_v3_cpu_interface.hh @@ -68,11 +68,11 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable Gicv3 * gic; Gicv3Redistributor * redistributor; Gicv3Distributor * distributor; - - ThreadContext *tc; - ArmInterruptPin *maintenanceInterrupt; uint32_t cpuId; + ArmInterruptPin *maintenanceInterrupt; + ThreadContext *tc; + BitUnion64(ICC_CTLR_EL1) Bitfield<63, 20> res0_3; Bitfield<19> ExtRange; @@ -359,7 +359,7 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable void setBankedMiscReg(ArmISA::MiscRegIndex misc_reg, RegVal val) const; public: - Gicv3CPUInterface(Gicv3 * gic, ThreadContext *tc); + Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id); void init(); @@ -369,6 +369,7 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable public: // BaseISADevice RegVal readMiscReg(int misc_reg) override; void setMiscReg(int misc_reg, RegVal val) override; + void setThreadContext(ThreadContext *tc) override; }; } // namespace gem5