derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

dev-amdgpu: Handle ring buffer wrap for PM4 queue

Browse Source 
Change-Id: I27bc274327838add709423b072d437c4e727a714
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65431
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
This commit is contained in:
Matthew Poremba
2022-11-08 14:24:32 -08:00
parent 90046bae6f
commit 623e2d3dac
4 changed files with 18 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/dev/amdgpu/pm4_mmio.hh
View File

@@ -60,6 +60,7 @@ namespace gem5
#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251
#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x1252
#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1253
#define mmCP_HQD_PQ_CONTROL 0x1256
#define mmCP_HQD_IB_CONTROL 0x125a
#define mmCP_HQD_PQ_WPTR_LO 0x127b
#define mmCP_HQD_PQ_WPTR_HI 0x127c

13
src/dev/amdgpu/pm4_packet_processor.cc
View File

@@ -147,8 +147,8 @@ PM4PacketProcessor::newQueue(QueueDesc *mqd, Addr offset,
gpuDevice->setDoorbellType(offset, qt);
DPRINTF(PM4PacketProcessor, "New PM4 queue %d, base: %p offset: %p, me: "
"%d, pipe %d queue: %d\n", id, q->base(), q->offset(), q->me(),
q->pipe(), q->queue());
"%d, pipe %d queue: %d size: %d\n", id, q->base(), q->offset(),
q->me(), q->pipe(), q->queue(), q->size());
}
void
@@ -790,6 +790,9 @@ PM4PacketProcessor::writeMMIO(PacketPtr pkt, Addr mmio_offset)
case mmCP_HQD_PQ_WPTR_POLL_ADDR_HI:
setHqdPqWptrPollAddrHi(pkt->getLE<uint32_t>());
break;
case mmCP_HQD_PQ_CONTROL:
setHqdPqControl(pkt->getLE<uint32_t>());
break;
case mmCP_HQD_IB_CONTROL:
setHqdIbCtrl(pkt->getLE<uint32_t>());
break;
@@ -911,6 +914,12 @@ PM4PacketProcessor::setHqdPqWptrPollAddrHi(uint32_t data)
kiq.hqd_pq_wptr_poll_addr_hi = data;
}
void
PM4PacketProcessor::setHqdPqControl(uint32_t data)
{
kiq.hqd_pq_control = data;
}
void
PM4PacketProcessor::setHqdIbCtrl(uint32_t data)
{

1
src/dev/amdgpu/pm4_packet_processor.hh
View File

@@ -171,6 +171,7 @@ class PM4PacketProcessor : public DmaVirtDevice
void setHqdPqRptrReportAddrHi(uint32_t data);
void setHqdPqWptrPollAddr(uint32_t data);
void setHqdPqWptrPollAddrHi(uint32_t data);
void setHqdPqControl(uint32_t data);
void setHqdIbCtrl(uint32_t data);
void setRbVmid(uint32_t data);
void setRbCntl(uint32_t data);

7
src/dev/amdgpu/pm4_queues.hh
View File

@@ -396,14 +396,14 @@ class PM4Queue
rptr()
{
if (ib()) return q->ibBase + q->ibRptr;
else return q->base + q->rptr;
else return q->base + (q->rptr % size());
}
Addr
wptr()
{
if (ib()) return q->ibBase + _ibWptr;
else return q->base + _wptr;
else return q->base + (_wptr % size());
}
Addr
@@ -470,6 +470,9 @@ class PM4Queue
uint32_t pipe() { return _pkt.pipe; }
uint32_t queue() { return _pkt.queueSlot; }
bool privileged() { return _pkt.queueSel == 0 ? 1 : 0; }
// Same computation as processMQD. See comment there for details.
uint64_t size() { return 4UL << ((q->hqd_pq_control & 0x3f) + 1); }
};
} // namespace gem5