mem: implement ThreadBridge
ThreadBridge is used for communication between two SimObjects from different threads (EventQueue). Change-Id: I3e00df9184404599dfacef64b505cd0b64ee46aa Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65071 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Yu-hsin Wang <yuhsingw@google.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Earl Ou
@@ -67,6 +67,7 @@ SimObject('HMCController.py', sim_objects=['HMCController'])
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SimObject('SerialLink.py', sim_objects=['SerialLink'])
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SimObject('MemDelay.py', sim_objects=['MemDelay', 'SimpleMemDelay'])
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SimObject('PortTerminator.py', sim_objects=['PortTerminator'])
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SimObject('ThreadBridge.py', sim_objects=['ThreadBridge'])
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Source('abstract_mem.cc')
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Source('addr_mapper.cc')
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@@ -93,6 +94,7 @@ Source('simple_mem.cc')
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Source('snoop_filter.cc')
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Source('stack_dist_calc.cc')
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Source('sys_bridge.cc')
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Source('thread_bridge.cc')
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Source('token_port.cc')
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Source('tport.cc')
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Source('xbar.cc')
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60
src/mem/ThreadBridge.py
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60
src/mem/ThreadBridge.py
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@@ -0,0 +1,60 @@
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# Copyright 2022 Google, LLC
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.SimObject import SimObject
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from m5.params import *
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class ThreadBridge(SimObject):
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"""Bridge for SimObjects from different threads (EventQueues)
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When two SimObjects running on two separate threads (EventQueues), an
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access from one side to the other side could easily cause event scheduled
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on the wrong event queue.
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ThreadBridge is used to migrate the EventQueue to the one used by
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ThreadBridge itself before sending transation to the other side to avoid
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the issue. The receiver side is expected to use the same EventQueue that
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the ThreadBridge is using.
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Given that this is only used for simulation speed accelerating, only the
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atomic and functional access are supported.
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Example:
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sys.initator = Initiator(eventq_index=0)
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sys.target = Target(eventq_index=1)
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sys.bridge = ThreadBridge(eventq_index=1)
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sys.initator.out_port = sys.bridge.in_port
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sys.bridge.out_port = sys.target.in_port
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"""
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type = "ThreadBridge"
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cxx_header = "mem/thread_bridge.hh"
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cxx_class = "gem5::ThreadBridge"
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in_port = ResponsePort("Incoming port")
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out_port = RequestPort("Outgoing port")
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121
src/mem/thread_bridge.cc
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121
src/mem/thread_bridge.cc
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@@ -0,0 +1,121 @@
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/*
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* Copyright 2022 Google, LLC
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "mem/thread_bridge.hh"
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#include "base/trace.hh"
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#include "sim/eventq.hh"
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namespace gem5
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{
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ThreadBridge::ThreadBridge(const ThreadBridgeParams &p)
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: SimObject(p), in_port_("in_port", *this), out_port_("out_port", *this)
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{
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}
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ThreadBridge::IncomingPort::IncomingPort(const std::string &name,
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ThreadBridge &device)
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: ResponsePort(name, &device), device_(device)
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{
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}
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AddrRangeList
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ThreadBridge::IncomingPort::getAddrRanges() const
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{
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return device_.out_port_.getAddrRanges();
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}
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// TimingResponseProtocol
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bool
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ThreadBridge::IncomingPort::recvTimingReq(PacketPtr pkt)
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{
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panic("ThreadBridge only supports atomic/functional access.");
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}
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void
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ThreadBridge::IncomingPort::recvRespRetry()
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{
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panic("ThreadBridge only supports atomic/functional access.");
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}
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// AtomicResponseProtocol
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Tick
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ThreadBridge::IncomingPort::recvAtomicBackdoor(PacketPtr pkt,
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MemBackdoorPtr &backdoor)
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{
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panic("ThreadBridge only supports atomic/functional access.");
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}
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Tick
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ThreadBridge::IncomingPort::recvAtomic(PacketPtr pkt)
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{
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EventQueue::ScopedMigration migrate(device_.eventQueue());
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return device_.out_port_.sendAtomic(pkt);
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}
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// FunctionalResponseProtocol
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void
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ThreadBridge::IncomingPort::recvFunctional(PacketPtr pkt)
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{
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EventQueue::ScopedMigration migrate(device_.eventQueue());
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device_.out_port_.sendFunctional(pkt);
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}
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ThreadBridge::OutgoingPort::OutgoingPort(const std::string &name,
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ThreadBridge &device)
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: RequestPort(name, &device), device_(device)
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{
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}
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void
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ThreadBridge::OutgoingPort::recvRangeChange()
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{
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device_.in_port_.sendRangeChange();
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}
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// TimingRequestProtocol
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bool
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ThreadBridge::OutgoingPort::recvTimingResp(PacketPtr pkt)
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{
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panic("ThreadBridge only supports atomic/functional access.");
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}
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void
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ThreadBridge::OutgoingPort::recvReqRetry()
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{
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panic("ThreadBridge only supports atomic/functional access.");
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}
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Port &
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ThreadBridge::getPort(const std::string &if_name, PortID idx)
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{
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if (if_name == "in_port")
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return in_port_;
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if (if_name == "out_port")
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return out_port_;
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return SimObject::getPort(if_name, idx);
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}
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} // namespace gem5
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88
src/mem/thread_bridge.hh
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88
src/mem/thread_bridge.hh
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@@ -0,0 +1,88 @@
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/*
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* Copyright 2022 Google, LLC.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEM_THREAD_BRIDGE_HH__
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#define __MEM_THREAD_BRIDGE_HH__
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#include "mem/port.hh"
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#include "params/ThreadBridge.hh"
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#include "sim/sim_object.hh"
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namespace gem5
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{
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class ThreadBridge : public SimObject
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{
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public:
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explicit ThreadBridge(const ThreadBridgeParams &p);
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Port &getPort(const std::string &if_name,
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PortID idx = InvalidPortID) override;
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private:
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class IncomingPort : public ResponsePort
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{
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public:
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IncomingPort(const std::string &name, ThreadBridge &device);
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AddrRangeList getAddrRanges() const override;
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// TimingResponseProtocol
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bool recvTimingReq(PacketPtr pkt) override;
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void recvRespRetry() override;
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// AtomicResponseProtocol
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Tick recvAtomicBackdoor(PacketPtr pkt,
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MemBackdoorPtr &backdoor) override;
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Tick recvAtomic(PacketPtr pkt) override;
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// FunctionalResponseProtocol
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void recvFunctional(PacketPtr pkt) override;
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private:
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ThreadBridge &device_;
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};
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class OutgoingPort : public RequestPort
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{
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public:
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OutgoingPort(const std::string &name, ThreadBridge &device);
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void recvRangeChange() override;
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// TimingRequestProtocol
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bool recvTimingResp(PacketPtr pkt) override;
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void recvReqRetry() override;
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private:
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ThreadBridge &device_;
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};
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IncomingPort in_port_;
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OutgoingPort out_port_;
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};
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} // namespace gem5
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#endif // __MEM_THREAD_BRIDGE_HH__
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