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  • c40c4450f5 util-docker: Remove GCC Version 9 from Dockerfiles Bobby R. Bruce 2023-11-13 01:29:56 -08:00
  • eaec1a7146 tests: Remove GCC-9 compiler test Bobby R. Bruce 2023-11-13 01:03:43 -08:00
  • f61d709321 mem-ruby: update RubyRequest print to include GPU fields (#537) Matt Sinclair 2023-11-13 01:12:25 -06:00
  • 1204267fd8 mem-ruby: SLICC Fixes to GLC Atomics in WB L2 (#397) Daniel Kouchekinia 2023-11-09 15:15:10 -06:00
  • fc80e7b8ec First PIM modifications Derek Christ 2023-11-09 15:43:35 +01:00
  • c13b79977c configs,ext,stdlib: Update DRAMSys integration Derek Christ 2023-11-02 09:12:29 +01:00
  • 0442c9a88c configs,ext: gem5 SST bridge calls m5.instantiate() in gem5 (#507) Bobby R. Bruce 2023-11-08 10:14:29 -08:00
  • 86131d4323 mem-ruby, gpu-compute: update GPU L1I$ MRU info (#530) Matt Sinclair 2023-11-08 12:13:15 -06:00
  • 1f1e15e48f arch-arm,kvm: Fix copy-paste error (#541) Giacomo Travaglini 2023-11-08 08:35:02 +00:00
  • f97adbaac7 python: Handle unicode characters in config files (#521) Zixian Cai 2023-11-08 03:59:42 +11:00
  • 10374f2f05 Fix calculation of compressed size in bytes (#534) Daniel Carvalho 2023-11-07 13:58:32 -03:00
  • 76279fef59 mem-ruby: update RubyRequest print to include GPU fields Matt Sinclair 2023-11-05 02:21:47 -06:00
  • e109076357 ext: removed SST deprecation notice from SimpleMem Kaustav Goswami 2023-10-26 18:46:01 -07:00
  • 2c229aa2ff configs,ext: gem5 SST bridge calls m5.instantiate() in gem5 Kaustav Goswami 2023-10-25 13:59:51 -07:00
  • 71973b386e gpu-compute,dev-hsa: ROCm 5.5+ support (#498) Jason Lowe-Power 2023-11-06 10:51:37 -08:00
  • e4cdd73a59 arch-riscv: Fix line length of CSRData declaration (#519) Yu-Cheng Chang 2023-11-07 02:26:08 +08:00
  • 42fd7ff894 stdlib, resources: Update JSON data in workload Harshil Patel 2023-11-03 13:54:30 -07:00
  • e362310f3d gpu-compute: Update GPR allocation counts Matthew Poremba 2023-10-27 13:20:56 -05:00
  • f07e0e7f5d gpu-compute: Read dispatch packet with timing DMA Matthew Poremba 2023-10-20 16:30:43 -05:00
  • 37da1c45f3 dev-amdgpu: Better handling for queue remapping Matthew Poremba 2023-10-13 14:59:56 -05:00
  • d05433b3f6 gpu-compute,dev-hsa: Send vendor packet completion signal Matthew Poremba 2023-10-21 12:36:35 -05:00
  • 68287604ee arch-riscv: Make Zicbom/Zicboz extensions optional in FS mode Hoa Nguyen 2023-10-30 02:41:26 +00:00
  • 7c6fcb3838 arch-riscv: Add all supporting Z extensions to RISC-V isa string Hoa Nguyen 2023-10-30 02:36:24 +00:00
  • f615ee4cd4 arch-riscv: Fix generateDisassembly for Store with 1 source reg Hoa Nguyen 2023-10-30 02:18:29 +00:00
  • 2521ba0664 arch-riscv: Fix implementation of CMO extension instructions Hoa Nguyen 2023-10-30 02:07:04 +00:00
  • 4fdfb96cad arch-riscv: Load function symbols for BootloaderKernelWorkload Hoa Nguyen 2023-10-29 03:47:40 +00:00
  • 6eca83d0fb base: Add ability to generate SymbolTable by filtering SymbolType Hoa Nguyen 2023-10-29 03:29:30 +00:00
  • 697cab0544 base,sim: Add the SymbolType field to the Symbol object Hoa Nguyen 2023-10-29 03:20:47 +00:00
  • d0113185c6 arch-riscv: Dynamically add V extension to device tree (#464) Jason Lowe-Power 2023-10-30 10:29:25 -07:00
  • 3d93584900 mem-ruby, stdlib: Far atomics fix (#514) Jason Lowe-Power 2023-10-30 09:59:49 -07:00
  • 0218103162 arch-riscv: Correct BootloaderKernelWorkload symbol table (#511) Hoa Nguyen 2023-10-30 09:56:10 -07:00
  • d131ff488e arch-arm: Set UNCACHEABLE flag in Request in SE mode (#515) Giacomo Travaglini 2023-10-30 10:43:22 +00:00
  • 1087041698 stdlib: Use near atomics in the CHI component nodes Giacomo Travaglini 2023-10-29 08:27:19 +00:00
  • 1b05c0050b mem-ruby: Clear the atomic log from the DataBlock in CHI Giacomo Travaglini 2023-10-28 22:59:51 +01:00
  • e496d29171 stdlib: Explicitly set alloc_on_atomic for the CHI example Giacomo Travaglini 2023-10-18 15:18:43 +01:00
  • 06bf783a85 arch-riscv: Move RVV implementation from header to source (#500) Jason Lowe-Power 2023-10-26 17:38:18 -07:00
  • ecc248c3c1 misc: Fix spelling error in MAINTAINERS.yaml (#475) Ivana Mitrovic 2023-10-26 08:27:32 -07:00
  • e561f3b6f1 arch-riscv: Move insts/vector from header to source Roger Chang 2023-10-24 15:29:40 +08:00
  • 62af678d5c arch-riscv: Move VArith implementations from header to source Roger Chang 2023-10-24 14:47:04 +08:00
  • 605ec6899e arch-riscv: Move VMem implementation from header to source Roger Chang 2023-08-29 19:53:26 +08:00
  • 60290c7c2f cpu: Branch Predictor Refactoring (#455) Andreas Sandberg 2023-10-26 09:15:11 +01:00
  • 50196863a4 stdlib,dev: Fix several hardcoded RISC-V ISA strings Hoa Nguyen 2023-10-15 19:54:22 -07:00
  • dce8d07703 stdlib: Turn off RVV for U74 core Hoa Nguyen 2023-10-15 19:42:35 -07:00
  • 4f72f6172a stdlib: Use the ISA string generator in the RiscvBoard Hoa Nguyen 2023-10-15 19:36:20 -07:00
  • a47ca9dadc arch-riscv: Add a function generating the ISA string Hoa Nguyen 2023-10-15 19:29:01 -07:00
  • b6ce2d0db8 misc: Add GitHub Runner API rate limiting (#497) Bobby R. Bruce 2023-10-24 14:51:31 -07:00
  • b670ed9fba util: Add 'sudo' to rm WORK_DIR command (#496) Bobby R. Bruce 2023-10-24 14:51:19 -07:00
  • ccbb85c67f cpu: Branch Predictor Refactoring David Schall 2023-10-17 15:16:54 +00:00
  • e9da8d67bd misc: Merge develop .github dir to stable (#495) Bobby R. Bruce 2023-10-20 11:43:29 -07:00
  • 6ddf8c94ee arch-arm: Fix KVM Failed to set register (0x603000000013808c) (#486) Giacomo Travaglini 2023-10-20 19:30:19 +01:00
  • 8b78e87f1b misc: Integrate a Capstone Disassembler in gem5 (#494) Boris Shingarov 2023-10-20 13:47:23 -04:00
  • cb56c67a8b misc: Fix weekly-tests.yaml container uris (#488) Bobby R. Bruce 2023-10-20 09:39:12 -07:00
  • b13102fcc4 scons: Explicit some config options HAVE_* to boolean type (#490) Giacomo Travaglini 2023-10-20 11:39:48 +01:00
  • 8233aa8a9b arch-arm: Implement a CapstoneDisassembler for Arm Giacomo Travaglini 2023-09-21 15:01:42 +01:00
  • 82675648c8 cpu: Implement a CapstoneDisassembler Giacomo Travaglini 2023-10-09 18:23:40 +01:00
  • 34336208b7 arch-arm: Disassemble through InstDisassembler in TarmacTracer Giacomo Travaglini 2023-09-22 13:05:10 +01:00
  • 27ce721ad3 arch-arm: Pass a reference of the parent tracer to TarmacContext Giacomo Travaglini 2023-09-22 12:56:22 +01:00
  • 81b6e296dd arch-arm: disassemble member variable not used by TarmacParser Giacomo Travaglini 2023-09-22 12:48:14 +01:00
  • 237bbf0e42 cpu: Disassemble through the InstDisassembler in the ExeTracer Giacomo Travaglini 2023-09-22 09:05:45 +01:00
  • 952c4f5eea cpu: Pass a reference of the parent tracer to the ExeTracerRecord Giacomo Travaglini 2023-09-22 09:01:09 +01:00
  • 2d85707a75 sim: Define an InstructionDisassembler SimObject Giacomo Travaglini 2023-09-22 08:59:43 +01:00
  • 069baed971 scons: Explicit the config option HAVE_PROTOBUF type boolean Roger Chang 2023-10-20 11:40:24 +08:00
  • 1a7014c653 scons: Explicit the config option HAVE_PKG_CONFIG type boolean Roger Chang 2023-10-20 11:37:59 +08:00
  • fe20f4ada6 scons: Explicit the config option HAVE_DEPRECATED_NAMESPACE type bool Roger Chang 2023-10-20 11:10:25 +08:00
  • 531067fffa mem,tests: Set Ruby Mem Test atomic percent to 0 (#489) Bobby R. Bruce 2023-10-19 15:38:38 -07:00
  • 73c48a4828 arch-riscv: Add dynamic VLEN and ELEN configuration support to RVV path (#171) Jason Lowe-Power 2023-10-19 07:41:39 -07:00
  • 1bb9bb3308 misc: Copy .github directory from develop to stable (#485) Bobby R. Bruce 2023-10-18 22:19:24 -07:00
  • 34314b3f92 misc: Add LULESH GPU tests (#256) Melissa Jost 2023-10-18 22:14:39 -07:00
  • 62e5198796 docker-images: Use GitHub Container Registry (#418) Bobby R. Bruce 2023-10-18 22:08:01 -07:00
  • edf1d69257 arch-riscv: Define vlwhole/vswhole mem acceses using vlen. Alvaro Moreno 2023-10-12 20:02:41 +02:00
  • bfb295ac3f util: cpt_upgrader fix vregs size for #PR171 Adrià Armejach 2023-10-04 14:49:01 +02:00
  • 52219e5e6f arch-riscv: Add elen configuration to vector config instructions Alvaro Moreno 2023-09-23 21:42:08 +02:00
  • 2c9fca7b60 arch-riscv: Add vlen configuration to vector instructions Alvaro Moreno 2023-08-09 12:39:03 +02:00
  • 8a20f20f79 arch-riscv: Add vlen component to decoder state Alvaro Moreno 2023-09-14 09:43:43 +02:00
  • 5d97cb8b0b arch-riscv: Define VLEN and ELEN through the ISA object Alvaro Moreno 2023-09-09 12:43:28 +02:00
  • 57e0ba7765 arch-riscv: Define VecRegContainer with maximum expected length Alvaro Moreno 2023-08-09 12:30:13 +02:00
  • be89758f0e misc: Add additional pre-commit hook checks (#420) Bobby R. Bruce 2023-10-18 12:21:22 -07:00
  • c3acfdc9b8 arch-riscv: Copy Misc Regs when swiching cpus (#479) Hoa Nguyen 2023-10-18 10:51:37 -07:00
  • 7bd0b99635 tests: Changed percent atomics to 0 in memtest to fix daily test (#477) Harshil Patel 2023-10-18 10:09:45 -07:00
  • 334df18dce arch-riscv: Add bootloader+kernel workload (#390) Bobby R. Bruce 2023-10-18 09:17:12 -07:00
  • e9fe9cb001 util: Improve GitHub Action runners: Enable KVM; Better Cleanup; Better Tooling (#470) Bobby R. Bruce 2023-10-17 11:38:40 -07:00
  • 42d1c8b3c3 cpu: Restructure RAS (#428) Andreas Sandberg 2023-10-17 19:14:13 +01:00
  • 5387e67114 cpu: Restructure RAS David Schall 2023-09-05 08:01:13 +00:00
  • 3783afff5d util: Enable KVM on VMs and ensure working in Runners Bobby R. Bruce 2023-10-16 21:21:31 -07:00
  • d18087af96 util: Add halt-helper.sh Bobby R. Bruce 2023-10-16 21:14:09 -07:00
  • adb5470996 arch-arm: Fix (other) line-length errors (#468) Bobby R. Bruce 2023-10-16 17:47:46 -07:00
  • 4b9c4e1e17 misc: Add --all to Runner docker system prune Bobby R. Bruce 2023-10-16 13:33:30 -07:00
  • cfef2ac23b util-docker: Fix end-of-line error in docker-bake.hcl Bobby R. Bruce 2023-10-16 12:06:01 -07:00
  • cb078f14c6 docker-bake: Changed compilers names to be more descriptive Ivana Mitrovic 2023-10-12 10:44:43 -07:00
  • 45df1dbb55 docker-images: Changed path from Google Registry to GitHub Ivana Mitrovic 2023-10-09 08:55:54 -07:00
  • 5b721b033f docker-bake: modified .hcl file Ivana Mitrovic 2023-10-05 11:23:38 -07:00
  • df471092d9 dockerfiles: multi-platform setup (#336) Ivana Mitrovic 2023-10-05 10:53:07 -07:00
  • aaefda3b08 arch-arm: Fix line-length error in branch64.is Bobby R. Bruce 2023-10-16 10:57:03 -07:00
  • d048ad34d6 arch-riscv: Change to VS bits to DIRTY for rvv insts changing vregs (#376) Hoa Nguyen 2023-10-16 10:07:40 -07:00
  • 2825bc1d55 misc: Add missing RISCV valid ISA option to README.md (#462) Yu-Cheng Chang 2023-10-17 00:45:28 +08:00
  • 9b2b6cd8d2 arch-riscv: Mark vector configuration insts as vector insts (#463) Hoa Nguyen 2023-10-16 09:40:09 -07:00
  • a9464a41f5 stdlib,resources: Generalize exception for request retry (#466) Bobby R. Bruce 2023-10-16 09:39:44 -07:00
  • 322b105b9d arch-arm: Fix (another) line-length error in misc.cc Bobby R. Bruce 2023-10-16 09:37:51 -07:00
  • 5240c07d3c util: Fix runners to extent to max disk size (#460) Bobby R. Bruce 2023-10-16 09:20:13 -07:00
  • 97f4b44dd3 arch-arm: Fix line-length error in misc.cc (#459) Bobby R. Bruce 2023-10-16 08:35:54 -07:00