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arch-riscv: Add elen configuration to vector config instructions

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This patch adds elen as a member of vector configuration instructions so it can be used with the especulative execution

Change-Id: Iaf79015717a006374c5198aaa36e050edde40cee
This commit is contained in:
Alvaro Moreno
2023-09-23 21:42:08 +02:00
committed by Adrià Armejach
parent 2c9fca7b60
commit 52219e5e6f
4 changed files with 25 additions and 7 deletions
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1
src/arch/riscv/decoder.cc
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@@ -43,6 +43,7 @@ Decoder::Decoder(const RiscvDecoderParams &p) : InstDecoder(p, &machInst)
{
ISA *isa = dynamic_cast<ISA*>(p.isa);
vlen = isa->getVecLenInBits();
elen = isa->getVecElemLenInBits();
reset();
}

1
src/arch/riscv/decoder.hh
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@@ -61,6 +61,7 @@ class Decoder : public InstDecoder
uint32_t machInst;
uint32_t vlen;
uint32_t elen;
virtual StaticInstPtr decodeInst(ExtMachInst mach_inst);

7
src/arch/riscv/insts/vector.hh
View File

@@ -69,12 +69,15 @@ class VConfOp : public RiscvStaticInst
uint64_t zimm10;
uint64_t zimm11;
uint64_t uimm;
VConfOp(const char *mnem, ExtMachInst _extMachInst, OpClass __opClass)
uint32_t elen;
VConfOp(const char *mnem, ExtMachInst _extMachInst,
uint32_t _elen, OpClass __opClass)
: RiscvStaticInst(mnem, _extMachInst, __opClass),
bit30(_extMachInst.bit30), bit31(_extMachInst.bit31),
zimm10(_extMachInst.zimm_vsetivli),
zimm11(_extMachInst.zimm_vsetvli),
uimm(_extMachInst.uimm_vsetivli)
uimm(_extMachInst.uimm_vsetivli),
elen(_elen)
{
this->flags[IsVector] = true;
}

23
src/arch/riscv/isa/formats/vector_conf.isa
View File

@@ -42,8 +42,8 @@ def format VConfOp(code, write_code, declare_class, branch_class, *flags) {{
branchTargetTemplate = eval(branch_class)
header_output = declareTemplate.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
decoder_output = VConfConstructor.subst(iop)
decode_block = VConfDecodeBlock.subst(iop)
exec_output = VConfExecute.subst(iop) + branchTargetTemplate.subst(iop)
}};
@@ -61,7 +61,7 @@ def template VSetVlDeclare {{
public:
/// Constructor.
%(class_name)s(ExtMachInst machInst);
%(class_name)s(ExtMachInst machInst, uint32_t elen);
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::unique_ptr<PCStateBase> branchTarget(
ThreadContext *tc) const override;
@@ -86,7 +86,7 @@ def template VSetiVliDeclare {{
public:
/// Constructor.
%(class_name)s(ExtMachInst machInst);
%(class_name)s(ExtMachInst machInst, uint32_t elen);
Fault execute(ExecContext *, trace::InstRecord *) const override;
std::unique_ptr<PCStateBase> branchTarget(
const PCStateBase &branch_pc) const override;
@@ -97,6 +97,19 @@ def template VSetiVliDeclare {{
};
}};
def template VConfConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst _machInst, uint32_t _elen)
: %(base_class)s("%(mnemonic)s", _machInst, _elen, %(op_class)s)
{
%(set_reg_idx_arr)s;
%(constructor)s;
}
}};
def template VConfDecodeBlock {{
return new %(class_name)s(machInst,elen);
}};
def template VConfExecute {{
VTYPE
%(class_name)s::getNewVtype(
@@ -112,7 +125,7 @@ def template VConfExecute {{
uint32_t newVill =
!(vflmul >= 0.125 && vflmul <= 8) ||
sew > std::min(vflmul, 1.0f) * ELEN ||
sew > std::min(vflmul, 1.0f) * elen ||
bits(reqVtype, 62, 8) != 0;
if (newVill) {
newVtype = 0;