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arch-riscv: Move VArith implementations from header to source

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Move VArith implementations from heaher_output to decoder_output
and exec_output respectively

Change-Id: I406eedbd9dd625aa939ec0e20aa29ef4f18ba79c
This commit is contained in:
Roger Chang
2023-10-24 14:47:04 +08:00
committed by Yu-Cheng Chang
parent 605ec6899e
commit 62af678d5c
2 changed files with 487 additions and 222 deletions
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564
src/arch/riscv/isa/formats/vector_arith.isa
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145
src/arch/riscv/isa/templates/vector_arith.isa
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@@ -107,6 +107,9 @@ template<typename ElemType>
this->microops.front()->setFirstMicroop();
this->microops.back()->setLastMicroop();
}
%(declare_varith_template)s;
}};
def template VectorIntMicroDeclare {{
@@ -145,6 +148,8 @@ template<typename ElemType>
%(set_src_reg_idx)s;
}
%(declare_varith_template)s;
}};
def template VectorIntMicroExecute {{
@@ -182,6 +187,8 @@ Fault
return NoFault;
}
%(declare_varith_template)s;
}};
def template VectorIntExtMacroDeclare {{
@@ -193,14 +200,7 @@ private:
public:
%(class_name)s(ExtMachInst _machInst, uint32_t _vlen);
std::string generateDisassembly(Addr pc,
const loader::SymbolTable *symtab) const override
{
std::stringstream ss;
ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", "
<< registerName(srcRegIdx(0));
if (machInst.vm == 0) ss << ", v0.t";
return ss.str();
}
const loader::SymbolTable *symtab) const override;
};
}};
@@ -219,14 +219,7 @@ public:
uint8_t _microIdx);
Fault execute(ExecContext* xc, trace::InstRecord* traceData)const override;
std::string generateDisassembly(Addr pc,
const loader::SymbolTable *symtab) const override
{
std::stringstream ss;
ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", "
<< registerName(srcRegIdx(0));
if (machInst.vm == 0) ss << ", v0.t";
return ss.str();
}
const loader::SymbolTable *symtab) const override;
};
}};
@@ -303,6 +296,38 @@ Fault
return NoFault;
}
template <typename ElemType>
std::string
%(class_name)s<ElemType>::generateDisassembly(Addr pc,
const loader::SymbolTable *symtab) const
{
std::stringstream ss;
ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", "
<< registerName(srcRegIdx(0));
if (machInst.vm == 0) ss << ", v0.t";
return ss.str();
}
%(declare_varith_template)s;
}};
def template VectorIntExtMacroExecute {{
template <typename ElemType>
std::string
%(class_name)s<ElemType>::generateDisassembly(Addr pc,
const loader::SymbolTable *symtab) const
{
std::stringstream ss;
ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", "
<< registerName(srcRegIdx(0));
if (machInst.vm == 0) ss << ", v0.t";
return ss.str();
}
%(declare_varith_template)s;
}};
def template VectorIntDecodeBlock {{
@@ -365,6 +390,8 @@ template<typename ElemType>
this->microops.back()->setLastMicroop();
}
%(declare_varith_template)s;
}};
def template VectorIntWideningMicroDeclare {{
@@ -402,6 +429,8 @@ template<typename ElemType>
%(set_src_reg_idx)s;
}
%(declare_varith_template)s;
}};
def template VectorIntWideningMicroExecute {{
@@ -447,6 +476,8 @@ Fault
return NoFault;
}
%(declare_varith_template)s;
}};
def template VectorIntNarrowingMicroExecute {{
@@ -493,6 +524,8 @@ Fault
return NoFault;
}
%(declare_varith_template)s;
}};
def template VectorIntWideningDecodeBlock {{
@@ -546,6 +579,9 @@ template<typename ElemType>
this->microops.front()->setFirstMicroop();
this->microops.back()->setLastMicroop();
}
%(declare_varith_template)s;
}};
def template VectorFloatMicroDeclare {{
@@ -582,6 +618,8 @@ template<typename ElemType>
%(set_src_reg_idx)s;
}
%(declare_varith_template)s;
}};
def template VectorFloatMicroExecute {{
@@ -620,6 +658,8 @@ Fault
return NoFault;
}
%(declare_varith_template)s;
}};
def template VectorFloatDecodeBlock {{
@@ -725,6 +765,8 @@ Fault
return NoFault;
}
%(declare_varith_template)s;
}};
def template VectorFloatNarrowingMicroExecute {{
@@ -772,6 +814,8 @@ Fault
return NoFault;
}
%(declare_varith_template)s;
}};
def template VectorFloatWideningDecodeBlock {{
@@ -826,6 +870,8 @@ template<typename ElemType>
this->microops.back()->setLastMicroop();
}
%(declare_varith_template)s;
}};
def template ViotaMicroDeclare {{
@@ -865,6 +911,8 @@ template<typename ElemType>
setSrcRegIdx(_numSrcRegs++, vecRegClass[_machInst.vs2]);
}
%(declare_varith_template)s;
}};
def template ViotaMicroExecute {{
@@ -899,6 +947,8 @@ Fault
return NoFault;
}
%(declare_varith_template)s;
}};
@@ -915,6 +965,8 @@ template<typename ElemType>
%(set_vm_idx)s;
}
%(declare_varith_template)s;
}};
def template Vector1Vs1VdMaskExecute {{
@@ -948,6 +1000,8 @@ Fault
return NoFault;
};
%(declare_varith_template)s;
}};
def template Vector1Vs1RdMaskDeclare {{
@@ -978,6 +1032,8 @@ template<typename ElemType>
%(set_vm_idx)s;
}
%(declare_varith_template)s;
}};
def template Vector1Vs1RdMaskExecute {{
@@ -1010,6 +1066,8 @@ Fault
return NoFault;
};
%(declare_varith_template)s;
}};
def template VectorIntMaskMacroDeclare {{
@@ -1057,6 +1115,8 @@ template<typename ElemType>
this->microops.back()->setLastMicroop();
}
%(declare_varith_template)s;
}};
def template VectorIntMaskMicroDeclare {{
@@ -1095,6 +1155,8 @@ template<typename ElemType>
%(set_src_reg_idx)s;
}
%(declare_varith_template)s;
}};
def template VectorIntMaskMicroExecute {{
@@ -1133,6 +1195,8 @@ Fault
return NoFault;
}
%(declare_varith_template)s;
}};
def template VectorFloatMaskMacroDeclare {{
@@ -1180,6 +1244,8 @@ template<typename ElemType>
this->microops.back()->setLastMicroop();
}
%(declare_varith_template)s;
}};
def template VectorFloatMaskMicroDeclare {{
@@ -1217,6 +1283,8 @@ template<typename ElemType>
%(set_src_reg_idx)s;
}
%(declare_varith_template)s;
}};
def template VectorFloatMaskMicroExecute {{
@@ -1255,6 +1323,8 @@ Fault
return NoFault;
}
%(declare_varith_template)s;
}};
def template VMvWholeMacroDeclare {{
@@ -1381,6 +1451,8 @@ template<typename ElemType>
%(set_src_reg_idx)s;
}
%(declare_varith_template)s;
}};
def template VectorMaskExecute {{
@@ -1415,6 +1487,8 @@ Fault
return NoFault;
};
%(declare_varith_template)s;
}};
def template VectorMaskDecodeBlock {{
@@ -1449,6 +1523,8 @@ template<typename ElemType>
%(set_vm_idx)s;
}
%(declare_varith_template)s;
}};
def template VectorIntNonSplitExecute {{
@@ -1481,6 +1557,8 @@ Fault
return NoFault;
}
%(declare_varith_template)s;
}};
def template VectorFloatNonSplitExecute {{
@@ -1513,6 +1591,8 @@ Fault
return NoFault;
}
%(declare_varith_template)s;
}};
def template VectorFloatNonSplitDecodeBlock {{
@@ -1578,6 +1658,8 @@ template<typename ElemType>
this->microops.back()->setLastMicroop();
}
%(declare_varith_template)s;
}};
def template VectorReduceMicroDeclare {{
@@ -1615,6 +1697,8 @@ template<typename ElemType>
%(set_src_reg_idx)s;
}
%(declare_varith_template)s;
}};
def template VectorReduceIntMicroExecute {{
@@ -1664,6 +1748,8 @@ Fault
return NoFault;
}
%(declare_varith_template)s;
}};
def template VectorReduceFloatMicroExecute {{
@@ -1715,6 +1801,8 @@ Fault
return NoFault;
}
%(declare_varith_template)s;
}};
def template VectorReduceFloatWideningMicroExecute {{
@@ -1765,6 +1853,8 @@ Fault
return NoFault;
}
%(declare_varith_template)s;
}};
def template VectorGatherMacroDeclare {{
@@ -1824,6 +1914,8 @@ template<typename ElemType, typename IndexType>
this->microops.back()->setLastMicroop();
}
%(declare_varith_template)s;
}};
def template VectorGatherMicroDeclare {{
@@ -1873,6 +1965,8 @@ template<typename ElemType, typename IndexType>
%(set_src_reg_idx)s;
}
%(declare_varith_template)s;
}};
def template VectorGatherMicroExecute {{
@@ -1930,6 +2024,8 @@ Fault
return NoFault;
}
%(declare_varith_template)s;
}};
def template VectorGatherDecodeBlock {{
@@ -2003,6 +2099,9 @@ template<typename ElemType>
this->microops.front()->setFirstMicroop();
this->microops.back()->setLastMicroop();
}
%(declare_varith_template)s;
}};
def template VectorIntVxsatMicroDeclare {{
@@ -2041,6 +2140,8 @@ template<typename ElemType>
%(set_src_reg_idx)s;
}
%(declare_varith_template)s;
}};
def template VectorReduceIntWideningMicroExecute {{
@@ -2094,6 +2195,8 @@ Fault
return NoFault;
}
%(declare_varith_template)s;
}};
def template VectorSlideMacroDeclare {{
@@ -2142,6 +2245,8 @@ template<typename ElemType>
this->microops.back()->setLastMicroop();
}
%(declare_varith_template)s;
}};
def template VectorSlideDownMacroConstructor {{
@@ -2177,6 +2282,8 @@ template<typename ElemType>
this->microops.back()->setLastMicroop();
}
%(declare_varith_template)s;
}};
def template VectorSlideMicroDeclare {{
@@ -2215,6 +2322,8 @@ template<typename ElemType>
%(set_src_reg_idx)s;
}
%(declare_varith_template)s;
}};
def template VectorSlideMicroExecute {{
@@ -2254,6 +2363,8 @@ Fault
return NoFault;
};
%(declare_varith_template)s;
}};
def template VectorFloatSlideMicroExecute {{
@@ -2293,4 +2404,6 @@ Fault
return NoFault;
};
%(declare_varith_template)s;
}};