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arch-riscv: Move VMem implementation from header to source

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Move the VMem implementation from header_output to
decoder_output and exec_output respectively.

Change-Id: I699e197f37f22a59ecb9f92a64b5e296d2e9f5fa
This commit is contained in:
Roger Chang
2023-08-29 19:53:26 +08:00
committed by Yu-Cheng Chang
parent 60290c7c2f
commit 605ec6899e
3 changed files with 216 additions and 136 deletions
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28
src/arch/riscv/isa/formats/vector_mem.isa
View File

@@ -34,6 +34,14 @@ def setVlen():
def setVlenb():
return "uint32_t vlenb = VlenbBits;\n"
def declareVMemTemplate(class_name):
return f'''
template class {class_name}<uint8_t>;
template class {class_name}<uint16_t>;
template class {class_name}<uint32_t>;
template class {class_name}<uint64_t>;
'''
def VMemBase(name, Name, ea_code, memacc_code, mem_flags,
inst_flags, base_class, postacc_code='',
declare_template_base=VMemMacroDeclare,
@@ -47,22 +55,20 @@ def VMemBase(name, Name, ea_code, memacc_code, mem_flags,
iop = InstObjParams(name, Name, base_class,
{'ea_code': ea_code,
'memacc_code': memacc_code,
'postacc_code': postacc_code },
'postacc_code': postacc_code,
'declare_vmem_template': declareVMemTemplate(Name)},
inst_flags)
constructTemplate = eval(exec_template_base + 'Constructor')
header_output = declare_template_base.subst(iop)
decoder_output = ''
if declare_template_base is not VMemTemplateMacroDeclare:
decoder_output += constructTemplate.subst(iop)
else:
header_output += constructTemplate.subst(iop)
decoder_output = constructTemplate.subst(iop)
decode_block = decode_template.subst(iop)
exec_output = ''
if not is_macroop:
return (header_output, decoder_output, decode_block, exec_output)
micro_class_name = exec_template_base + 'MicroInst'
microiop = InstObjParams(name + '_micro',
Name + 'Micro',
exec_template_base + 'MicroInst',
@@ -70,7 +76,8 @@ def VMemBase(name, Name, ea_code, memacc_code, mem_flags,
'memacc_code': memacc_code,
'postacc_code': postacc_code,
'set_vlenb': setVlenb(),
'set_vlen': setVlen()},
'set_vlen': setVlen(),
'declare_vmem_template': declareVMemTemplate(Name + 'Micro')},
inst_flags)
if mem_flags:
@@ -79,17 +86,16 @@ def VMemBase(name, Name, ea_code, memacc_code, mem_flags,
microiop.constructor += s
microDeclTemplate = eval(exec_template_base + 'Micro' + 'Declare')
microConsTemplate = eval(exec_template_base + 'Micro' + 'Constructor')
microExecTemplate = eval(exec_template_base + 'Micro' + 'Execute')
microInitTemplate = eval(exec_template_base + 'Micro' + 'InitiateAcc')
microCompTemplate = eval(exec_template_base + 'Micro' + 'CompleteAcc')
header_output = microDeclTemplate.subst(microiop) + header_output
decoder_output = microConsTemplate.subst(microiop) + decoder_output
micro_exec_output = (microExecTemplate.subst(microiop) +
microInitTemplate.subst(microiop) +
microCompTemplate.subst(microiop))
if declare_template_base is not VMemTemplateMacroDeclare:
exec_output += micro_exec_output
else:
header_output += micro_exec_output
exec_output += micro_exec_output
return (header_output, decoder_output, decode_block, exec_output)

2
src/arch/riscv/isa/includes.isa
View File

@@ -46,8 +46,6 @@ output header {{
#include <softfloat.h>
#include <specialize.h>
#include "arch/generic/memhelpers.hh"
#include "arch/riscv/decoder.hh"
#include "arch/riscv/insts/amo.hh"
#include "arch/riscv/insts/bs.hh"
#include "arch/riscv/insts/compressed.hh"

322
src/arch/riscv/isa/templates/vector_mem.isa
View File

@@ -96,22 +96,8 @@ private:
RegId srcRegIdxArr[3];
RegId destRegIdxArr[1];
public:
%(class_name)s(ExtMachInst _machInst, uint32_t _microVl,
uint8_t _microIdx, uint32_t _vlen)
: %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s,
_microVl, _microIdx, _vlen)
{
%(set_reg_idx_arr)s;
_numSrcRegs = 0;
_numDestRegs = 0;
setDestRegIdx(_numDestRegs++, vecRegClass[_machInst.vd + _microIdx]);
_numTypedDestRegs[VecRegClass]++;
setSrcRegIdx(_numSrcRegs++, intRegClass[_machInst.rs1]);
setSrcRegIdx(_numSrcRegs++, vecRegClass[_machInst.vd + _microIdx]);
if (!_machInst.vm) {
setSrcRegIdx(_numSrcRegs++, vecRegClass[0]);
}
}
%(class_name)s(ExtMachInst _machInst, uint8_t _microVl,
uint8_t _microIdx, uint32_t _vlen);
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
@@ -123,6 +109,27 @@ public:
}};
def template VleMicroConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst _machInst, uint8_t _microVl,
uint8_t _microIdx, uint32_t _vlen)
: %(base_class)s(
"%(mnemonic)s", _machInst, %(op_class)s, _microVl, _microIdx, _vlen)
{
%(set_reg_idx_arr)s;
_numSrcRegs = 0;
_numDestRegs = 0;
setDestRegIdx(_numDestRegs++, vecRegClass[_machInst.vd + _microIdx]);
_numTypedDestRegs[VecRegClass]++;
setSrcRegIdx(_numSrcRegs++, intRegClass[_machInst.rs1]);
setSrcRegIdx(_numSrcRegs++, vecRegClass[_machInst.vd + _microIdx]);
if (!_machInst.vm) {
setSrcRegIdx(_numSrcRegs++, vecRegClass[0]);
}
}
}};
def template VleMicroExecute {{
Fault
@@ -293,21 +300,7 @@ private:
RegId destRegIdxArr[0];
public:
%(class_name)s(ExtMachInst _machInst,
uint32_t _microVl, uint8_t _microIdx, uint32_t _vlen)
: %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s,
_microVl, _microIdx, _vlen)
{
%(set_reg_idx_arr)s;
_numSrcRegs = 0;
_numDestRegs = 0;
setSrcRegIdx(_numSrcRegs++, intRegClass[_machInst.rs1]);
setSrcRegIdx(_numSrcRegs++, vecRegClass[_machInst.vs3 + _microIdx]);
if (!_machInst.vm) {
setSrcRegIdx(_numSrcRegs++, vecRegClass[0]);
}
this->flags[IsVector] = true;
this->flags[IsStore] = true;
}
uint8_t _microVl, uint8_t _microIdx, uint32_t _vlen);
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
@@ -318,6 +311,27 @@ public:
}};
def template VseMicroConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst _machInst,
uint8_t _microVl, uint8_t _microIdx, uint32_t _vlen)
: %(base_class)s(
"%(mnemonic)s", _machInst, %(op_class)s, _microVl, _microIdx, _vlen)
{
%(set_reg_idx_arr)s;
_numSrcRegs = 0;
_numDestRegs = 0;
setSrcRegIdx(_numSrcRegs++, intRegClass[_machInst.rs1]);
setSrcRegIdx(_numSrcRegs++, vecRegClass[_machInst.vs3 + _microIdx]);
if (!_machInst.vm) {
setSrcRegIdx(_numSrcRegs++, vecRegClass[0]);
}
this->flags[IsVector] = true;
this->flags[IsStore] = true;
}
}};
def template VseMicroExecute {{
Fault
@@ -518,18 +532,8 @@ private:
RegId srcRegIdxArr[2];
public:
%(class_name)s(ExtMachInst _machInst,
uint32_t _microVl, uint8_t _microIdx, uint32_t _vlen)
: %(base_class)s("%(mnemonic)s", _machInst,
%(op_class)s, _microVl, _microIdx, _vlen)
{
%(set_reg_idx_arr)s;
_numSrcRegs = 0;
_numDestRegs = 0;
setSrcRegIdx(_numSrcRegs++, intRegClass[_machInst.rs1]);
setSrcRegIdx(_numSrcRegs++, vecRegClass[_machInst.vs3 + _microIdx]);
this->flags[IsVector] = true;
this->flags[IsStore] = true;
}
uint8_t _microVl, uint8_t _microIdx, uint32_t _vlen);
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
@@ -539,6 +543,24 @@ public:
}};
def template VsWholeMicroConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst _machInst,
uint8_t _microVl, uint8_t _microIdx, uint32_t _vlen)
: %(base_class)s(
"%(mnemonic)s", _machInst, %(op_class)s, _microVl, _microIdx, _vlen)
{
%(set_reg_idx_arr)s;
_numSrcRegs = 0;
_numDestRegs = 0;
setSrcRegIdx(_numSrcRegs++, intRegClass[_machInst.rs1]);
setSrcRegIdx(_numSrcRegs++, vecRegClass[_machInst.vs3 + _microIdx]);
this->flags[IsVector] = true;
this->flags[IsStore] = true;
}
}};
def template VsWholeMicroExecute {{
Fault
@@ -644,19 +666,8 @@ private:
RegId srcRegIdxArr[1];
public:
%(class_name)s(ExtMachInst _machInst,
uint32_t _microVl, uint8_t _microIdx, uint32_t _vlen)
: %(base_class)s("%(mnemonic)s_micro", _machInst,
%(op_class)s, _microVl, _microIdx, _vlen)
{
%(set_reg_idx_arr)s;
_numSrcRegs = 0;
_numDestRegs = 0;
setDestRegIdx(_numDestRegs++, vecRegClass[_machInst.vd + _microIdx]);
_numTypedDestRegs[VecRegClass]++;
setSrcRegIdx(_numSrcRegs++, intRegClass[_machInst.rs1]);
this->flags[IsVector] = true;
this->flags[IsLoad] = true;
}
uint8_t _microVl, uint8_t _microIdx, uint32_t _vlen);
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
@@ -666,6 +677,25 @@ public:
}};
def template VlWholeMicroConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst _machInst,
uint8_t _microVl, uint8_t _microIdx, uint32_t _vlen)
: %(base_class)s("%(mnemonic)s_micro", _machInst, %(op_class)s, _microVl,
_microIdx, _vlen)
{
%(set_reg_idx_arr)s;
_numSrcRegs = 0;
_numDestRegs = 0;
setDestRegIdx(_numDestRegs++, vecRegClass[_machInst.vd + _microIdx]);
_numTypedDestRegs[VecRegClass]++;
setSrcRegIdx(_numSrcRegs++, intRegClass[_machInst.rs1]);
this->flags[IsVector] = true;
this->flags[IsLoad] = true;
}
}};
def template VlWholeMicroExecute {{
Fault
@@ -803,24 +833,7 @@ private:
RegId destRegIdxArr[1];
public:
%(class_name)s(ExtMachInst _machInst, uint8_t _regIdx, uint8_t _microIdx,
uint32_t _microVl)
: %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s,
_regIdx, _microIdx, _microVl)
{
%(set_reg_idx_arr)s;
_numSrcRegs = 0;
_numDestRegs = 0;
setDestRegIdx(_numDestRegs++, vecRegClass[_machInst.vd + _regIdx]);
_numTypedDestRegs[VecRegClass]++;
setSrcRegIdx(_numSrcRegs++, intRegClass[_machInst.rs1]);
setSrcRegIdx(_numSrcRegs++, intRegClass[_machInst.rs2]);
// We treat agnostic as undistrubed
setSrcRegIdx(_numSrcRegs++, vecRegClass[_machInst.vd + _regIdx]);
if (!_machInst.vm) {
setSrcRegIdx(_numSrcRegs++, vecRegClass[0]);
}
this->flags[IsLoad] = true;
}
uint32_t _microVl);
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
@@ -831,6 +844,31 @@ public:
}};
def template VlStrideMicroConstructor {{
%(class_name)s::%(class_name)s(
ExtMachInst _machInst, uint8_t _regIdx, uint8_t _microIdx,
uint32_t _microVl)
: %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s,
_regIdx, _microIdx, _microVl)
{
%(set_reg_idx_arr)s;
_numSrcRegs = 0;
_numDestRegs = 0;
setDestRegIdx(_numDestRegs++, vecRegClass[_machInst.vd + _regIdx]);
_numTypedDestRegs[VecRegClass]++;
setSrcRegIdx(_numSrcRegs++, intRegClass[_machInst.rs1]);
setSrcRegIdx(_numSrcRegs++, intRegClass[_machInst.rs2]);
// We treat agnostic as undistrubed
setSrcRegIdx(_numSrcRegs++, vecRegClass[_machInst.vd + _regIdx]);
if (!_machInst.vm) {
setSrcRegIdx(_numSrcRegs++, vecRegClass[0]);
}
this->flags[IsLoad] = true;
}
}};
def template VlStrideMicroExecute {{
Fault
@@ -1019,21 +1057,7 @@ private:
RegId destRegIdxArr[0];
public:
%(class_name)s(ExtMachInst _machInst, uint8_t _regIdx, uint8_t _microIdx,
uint32_t _microVl)
: %(base_class)s("%(mnemonic)s""_micro", _machInst, %(op_class)s,
_regIdx, _microIdx, _microVl)
{
%(set_reg_idx_arr)s;
_numSrcRegs = 0;
_numDestRegs = 0;
setSrcRegIdx(_numSrcRegs++, intRegClass[_machInst.rs1]);
setSrcRegIdx(_numSrcRegs++, intRegClass[_machInst.rs2]);
setSrcRegIdx(_numSrcRegs++, vecRegClass[_machInst.vs3 + _regIdx]);
if (!_machInst.vm) {
setSrcRegIdx(_numSrcRegs++, vecRegClass[0]);
}
this->flags[IsStore] = true;
}
uint32_t _microVl);
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
@@ -1044,6 +1068,28 @@ public:
}};
def template VsStrideMicroConstructor {{
%(class_name)s::%(class_name)s(
ExtMachInst _machInst, uint8_t _regIdx, uint8_t _microIdx,
uint32_t _microVl)
: %(base_class)s("%(mnemonic)s""_micro", _machInst, %(op_class)s,
_regIdx, _microIdx, _microVl)
{
%(set_reg_idx_arr)s;
_numSrcRegs = 0;
_numDestRegs = 0;
setSrcRegIdx(_numSrcRegs++, intRegClass[_machInst.rs1]);
setSrcRegIdx(_numSrcRegs++, intRegClass[_machInst.rs2]);
setSrcRegIdx(_numSrcRegs++, vecRegClass[_machInst.vs3 + _regIdx]);
if (!_machInst.vm) {
setSrcRegIdx(_numSrcRegs++, vecRegClass[0]);
}
this->flags[IsStore] = true;
}
}};
def template VsStrideMicroExecute {{
Fault
@@ -1185,6 +1231,8 @@ template<typename ElemType>
this->flags[IsVector] = true;
}
%(declare_vmem_template)s;
}};
def template VlIndexMicroDeclare {{
@@ -1199,24 +1247,7 @@ private:
public:
%(class_name)s(ExtMachInst _machInst,
uint8_t _vdRegIdx, uint8_t _vdElemIdx,
uint8_t _vs2RegIdx, uint8_t _vs2ElemIdx)
: %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s,
_vdRegIdx, _vdElemIdx, _vs2RegIdx, _vs2ElemIdx)
{
%(set_reg_idx_arr)s;
_numSrcRegs = 0;
_numDestRegs = 0;
setDestRegIdx(_numDestRegs++, vecRegClass[_machInst.vd + _vdRegIdx]);
_numTypedDestRegs[VecRegClass]++;
setSrcRegIdx(_numSrcRegs++, intRegClass[_machInst.rs1]);
setSrcRegIdx(_numSrcRegs++, vecRegClass[_machInst.vs2 + _vs2RegIdx]);
// We treat agnostic as undistrubed
setSrcRegIdx(_numSrcRegs++, vecRegClass[_machInst.vd + _vdRegIdx]);
if (!_machInst.vm) {
setSrcRegIdx(_numSrcRegs++, vecRegClass[0]);
}
this->flags[IsLoad] = true;
}
uint8_t _vs2RegIdx, uint8_t _vs2ElemIdx);
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
@@ -1227,6 +1258,34 @@ public:
}};
def template VlIndexMicroConstructor {{
template<typename ElemType>
%(class_name)s<ElemType>::%(class_name)s(
ExtMachInst _machInst,uint8_t _vdRegIdx, uint8_t _vdElemIdx,
uint8_t _vs2RegIdx, uint8_t _vs2ElemIdx)
: %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s,
_vdRegIdx, _vdElemIdx, _vs2RegIdx, _vs2ElemIdx)
{
%(set_reg_idx_arr)s;
_numSrcRegs = 0;
_numDestRegs = 0;
setDestRegIdx(_numDestRegs++, vecRegClass[_machInst.vd + _vdRegIdx]);
_numTypedDestRegs[VecRegClass]++;
setSrcRegIdx(_numSrcRegs++, intRegClass[_machInst.rs1]);
setSrcRegIdx(_numSrcRegs++, vecRegClass[_machInst.vs2 + _vs2RegIdx]);
// We treat agnostic as undistrubed
setSrcRegIdx(_numSrcRegs++, vecRegClass[_machInst.vd + _vdRegIdx]);
if (!_machInst.vm) {
setSrcRegIdx(_numSrcRegs++, vecRegClass[0]);
}
this->flags[IsLoad] = true;
}
%(declare_vmem_template)s;
}};
def template VlIndexMicroExecute {{
template<typename ElemType>
@@ -1364,6 +1423,8 @@ Fault
return NoFault;
}
%(declare_vmem_template)s;
}};
def template VsIndexConstructor {{
@@ -1410,6 +1471,8 @@ template<typename ElemType>
this->flags[IsVector] = true;
}
%(declare_vmem_template)s;
}};
def template VsIndexMicroDeclare {{
@@ -1424,22 +1487,7 @@ private:
public:
%(class_name)s(ExtMachInst _machInst,
uint8_t _vs3RegIdx, uint8_t _vs3ElemIdx,
uint8_t _vs2RegIdx, uint8_t _vs2ElemIdx)
: %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s,
_vs3RegIdx, _vs3ElemIdx, _vs2RegIdx, _vs2ElemIdx)
{
%(set_reg_idx_arr)s;
_numSrcRegs = 0;
_numDestRegs = 0;
setSrcRegIdx(_numSrcRegs++, intRegClass[_machInst.rs1]);
setSrcRegIdx(_numSrcRegs++, vecRegClass[_machInst.vs2 + _vs2RegIdx]);
// We treat agnostic as undistrubed
setSrcRegIdx(_numSrcRegs++, vecRegClass[_machInst.vs3 + _vs3RegIdx]);
if (!_machInst.vm) {
setSrcRegIdx(_numSrcRegs++, vecRegClass[0]);
}
this->flags[IsStore] = true;
}
uint8_t _vs2RegIdx, uint8_t _vs2ElemIdx);
Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
@@ -1450,6 +1498,32 @@ public:
}};
def template VsIndexMicroConstructor {{
template<typename ElemType>
%(class_name)s<ElemType>::%(class_name)s(ExtMachInst _machInst,
uint8_t _vs3RegIdx, uint8_t _vs3ElemIdx,
uint8_t _vs2RegIdx, uint8_t _vs2ElemIdx)
: %(base_class)s("%(mnemonic)s", _machInst, %(op_class)s,
_vs3RegIdx, _vs3ElemIdx, _vs2RegIdx, _vs2ElemIdx)
{
%(set_reg_idx_arr)s;
_numSrcRegs = 0;
_numDestRegs = 0;
setSrcRegIdx(_numSrcRegs++, intRegClass[_machInst.rs1]);
setSrcRegIdx(_numSrcRegs++, vecRegClass[_machInst.vs2 + _vs2RegIdx]);
// We treat agnostic as undistrubed
setSrcRegIdx(_numSrcRegs++, vecRegClass[_machInst.vs3 + _vs3RegIdx]);
if (!_machInst.vm) {
setSrcRegIdx(_numSrcRegs++, vecRegClass[0]);
}
this->flags[IsStore] = true;
}
%(declare_vmem_template)s;
}};
def template VsIndexMicroExecute {{
template<typename ElemType>
@@ -1548,6 +1622,8 @@ Fault
return NoFault;
}
%(declare_vmem_template)s;
}};
def template VMemBaseDecodeBlock {{