derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Commit Graph

  • 529423f47a util: Remove note about ssh use Bobby R. Bruce 2023-10-04 17:37:11 -07:00
  • a924fa3bdc util: Add action-run.sh to run Action Runners Bobby R. Bruce 2023-10-04 17:21:13 -07:00
  • 3e1c0b0714 util: Move runners from gem5 repository to gem5 org Bobby R. Bruce 2023-10-04 15:18:45 -07:00
  • d1f9f98747 util: Make all runners the same type Bobby R. Bruce 2023-10-04 15:07:16 -07:00
  • 7a0e84d853 cpu-kvm, arch-x86: flush TLB after syscalls Nicholas Mosier 2023-10-06 20:41:59 +00:00
  • 0dcf0fb829 sim-se: unmap reclaimed heap pages in brk syscall emulation Nicholas Mosier 2023-09-21 16:06:31 +00:00
  • 75a7f30dfb dev-amdgpu: Implement GPU clock MMIOs Matthew Poremba 2023-10-06 13:02:31 -05:00
  • 6a4b2bb096 dev-hsa,gpu-compute: Add timestamps to AMD HSA signals Matthew Poremba 2023-09-11 09:22:26 -05:00
  • 00748c7901 mem-ruby: Fix CHI fromSequencer helper function Giacomo Travaglini 2023-10-06 14:48:51 +01:00
  • ae104cc431 mem-ruby: Add new feature far atomics in CHI (#177) Giacomo Travaglini 2023-10-06 10:09:58 +01:00
  • 6f8b74ece8 dev,arch-riscv: Mark gem5's 8250 UART as 16550a compatible Hoa Nguyen 2023-10-06 00:48:12 -07:00
  • 3fc6b67974 arch-riscv: Add several inform() to RiscvISA::BootloaderKernelWorkload Hoa Nguyen 2023-10-06 00:45:21 -07:00
  • e8fd8303fb stdlib: Add chosen node to the device tree of RISC-V board Hoa Nguyen 2023-10-05 23:15:27 -07:00
  • 46a9d85215 arch-riscv: Add bootloader+kernel workload Hoa Nguyen 2023-10-04 00:56:48 -07:00
  • a19667427a mem-ruby: Add BUILD_GPU guard to ruby cooldown and warmup phases Vishnu Ramadas 2023-10-05 18:59:54 -05:00
  • 85340973bf configs: Add configurable GPU L1,L2 num banks and L2 latencies (#389) Matt Sinclair 2023-10-05 15:54:24 -05:00
  • 4db748a507 resources, stdlib: Adding 'suite' category to gem5 (#191) Bobby R. Bruce 2023-10-05 13:26:58 -07:00
  • 761f6b73a0 arch-arm: Implement FEAT_FGT (#334) Bobby R. Bruce 2023-10-05 10:44:26 -07:00
  • f5c7ea01ef gpu-compute: Fix dynamic scratch size test (#391) Bobby R. Bruce 2023-10-05 10:38:13 -07:00
  • ee8c569513 arch-riscv: Implement Zcb instructions (#399) Bobby R. Bruce 2023-10-05 10:36:02 -07:00
  • f75c0fca8a stdlib: Del comment stating SE mode limited to single thread Bobby R. Bruce 2023-10-05 10:20:55 -07:00
  • 06bbc43b46 ext: Remove std::binary_function from DramPower Bobby R. Bruce 2023-10-05 07:25:04 -07:00
  • 39c7e7d1ed arch: Adding missing override to PCState.set Bobby R. Bruce 2023-10-04 11:37:04 -07:00
  • ea3ee880aa arch-riscv: Implement Zcb instructions Roger Chang 2023-07-05 16:11:14 +08:00
  • 98a6cd6ee2 misc: changed call get_default_disk_device to get_disk_device Leo Redivo 2023-10-04 13:32:35 -07:00
  • 6411b2255c mem-ruby,configs: Add CHI far atomics support Víctor Soria 2023-08-10 17:04:17 +02:00
  • 12dada2dc5 arch-arm: Correct return operand in swap instructions Víctor Soria 2023-07-24 16:25:08 +02:00
  • 4fd9d66c53 tests,mem-ruby: Enhance ruby false sharing test with Atomics Víctor Soria 2023-07-24 16:20:10 +02:00
  • 6f5d877b1a misc: Update gem5 to use clang-15 and clang-16 (#365) Jason Lowe-Power 2023-10-04 09:51:12 -07:00
  • 2b97f17fe1 gpu-compute: Fix dynamic scratch size test Matthew Poremba 2023-10-04 09:09:56 -05:00
  • 7806eaad51 arch: Add instruction size and PC set methods (#357) Andreas Sandberg 2023-10-04 10:49:30 +01:00
  • 57e0c7d006 arch-riscv: FS bits -> DIRTY for more floating point loads (#381) Bobby R. Bruce 2023-10-03 11:51:47 -07:00
  • d3637a489d configs: Add option to disable AVX in GPUFS Vishnu Ramadas 2023-10-03 12:10:42 -05:00
  • 53627cc39c configs: Add configurable GPU L1,L2 num banks and L2 latencies Vishnu Ramadas 2023-10-03 11:36:11 -05:00
  • 3af3c1121b stdlib, resources: Addressed requested changes Harshil Patel 2023-10-02 23:27:32 -07:00
  • f69191a31d dev-amdgpu: Remove duplicate writes to PM4 queue pointers Vishnu Ramadas 2023-10-02 19:37:46 -05:00
  • ae5a51994c mem-ruby: Update cache recorder to use GPUCoalescer port for GPUs Vishnu Ramadas 2023-09-29 18:27:46 -05:00
  • 085789d00c mem-ruby: Add flush support to GPU_VIPER protocol Vishnu Ramadas 2023-09-29 18:19:37 -05:00
  • 61e39d5b26 mem-ruby: Add cache cooldown and warmup support to GPUCoalescer Vishnu Ramadas 2023-09-29 16:37:41 -05:00
  • a50ead5907 mem-ruby: Add Flush as a supported memory type in VIPERCoalescer Vishnu Ramadas 2023-09-29 16:32:22 -05:00
  • 107e05266d dev-amdgpu: Add aql, hsa queue information to checkpoint-restore Vishnu Ramadas 2023-09-29 14:29:47 -05:00
  • 7301d4bd19 python: Add importer to standalone gem5py_m5 (#369) Harshil Patel 2023-10-02 14:28:45 -07:00
  • 7d2e1ee789 arch: Add instruction size and PC set methods David Schall 2023-06-27 08:46:39 +00:00
  • da72590c19 arch-riscv: FS bits -> DIRTY for more floating point loads Hoa Nguyen 2023-10-01 22:52:07 -07:00
  • e211674625 util-docker: Fix/Improve ubuntu-22.04_clang-16 Bobby R. Bruce 2023-09-29 13:12:19 -07:00
  • f9781af6e5 mem: fix bug in 3-level cache (#265) Harshil Patel 2023-09-29 10:59:18 -07:00
  • 2b791ff556 misc: fix g++13 overloaded-virtual warning (#363) Bobby R. Bruce 2023-09-29 10:53:52 -07:00
  • 8182f8084b stdlib, resources, tests: Introduce Suite of Workloads Harshil Patel 2023-08-16 15:14:19 -07:00
  • 3a35bdf57a arch-riscv: Update FS bits when doing floating point loads (#370) Bobby R. Bruce 2023-09-29 10:47:05 -07:00
  • a79dc3f23c util: Add steps to compile clang-15 and clang-16 Melissa Jost 2023-09-27 09:38:39 -07:00
  • 6640447c1e arch-riscv: Update FS bits when doing floating point loads Hoa Nguyen 2023-09-28 19:14:29 -07:00
  • aaad79cf51 python: Add importer to standalone gem5py_m5 Jason Lowe-Power 2023-08-14 16:15:50 -07:00
  • 62d34ef374 misc: 'sim{out/err}' -> 'sim{out/err}.txt' (#250) Bobby R. Bruce 2023-09-27 17:36:03 -07:00
  • 5d254ffb02 stdlib, resources: Added pretty printing resource (#323) Bobby R. Bruce 2023-09-27 17:32:35 -07:00
  • 14b928f77c base: Add a warning when failing to insert a whole symbol table (#361) Bobby R. Bruce 2023-09-27 17:26:03 -07:00
  • 074fa4c604 misc,ext,tests: Automatically split CI TestLib tests across GitHub Action jobs (#263) Bobby R. Bruce 2023-09-27 14:32:16 -07:00
  • 3a0f4598b9 cpu-o3: Mark getWritableRegOperand() in O3CPU as a regwrite (#360) Bobby R. Bruce 2023-09-27 14:31:38 -07:00
  • 49a1d48264 arch-x86: properly initialize the auxv platform string (#347) Bobby R. Bruce 2023-09-27 14:31:19 -07:00
  • 4638434b97 arch-x86: make popx87 micro-op actually pop st(0) (#345) Bobby R. Bruce 2023-09-27 14:31:00 -07:00
  • 633bdc08f2 stdlib: Addressed requested changes Harshil Patel 2023-09-27 11:36:51 -07:00
  • 34c3676105 misc: Update gem5 to use clang-15 and clang-16 Melissa Jost 2023-09-27 09:33:53 -07:00
  • 9ca2672cab misc: fix g++13 overloaded-virtual warning Yu-hsin Wang 2023-09-27 12:48:26 +08:00
  • cfa13f9feb sim: Probe listener template with lambda (#356) Andreas Sandberg 2023-09-26 10:08:24 +01:00
  • f5968da41c mem-ruby: start using txnid and DBID identifiers in CHI transactions (#288) Giacomo Travaglini 2023-09-26 09:51:47 +01:00
  • 91e55d9c60 base: Add warning when failing to insert a whole symbol table Hoa Nguyen 2023-09-25 16:23:17 -07:00
  • b759f22cc9 cpu-o3: Mark getWritableRegOperand() in O3CPU as a regwrite Hoa Nguyen 2023-09-25 12:29:28 -07:00
  • 010ac43369 arch-riscv: Make RISC-V decodeInst overridable (#350) Jason Lowe-Power 2023-09-25 06:43:56 -07:00
  • 7cb308db90 sim: Probe listener template with lambda David Schall 2023-06-26 18:46:01 +00:00
  • 9d63a1492a cpu: Add override to TraceCPU init function (#348) Giacomo Travaglini 2023-09-25 09:10:33 +01:00
  • 83224e2c85 arch: Enable customized decoder class name (#351) Giacomo Travaglini 2023-09-25 09:10:06 +01:00
  • df60b0f5c9 arch-arm: Implement FEAT_FGT Giacomo Travaglini 2023-04-17 13:44:11 +01:00
  • 37b6824c4c arch-arm: Fix disassembly for NZCV read/writes Giacomo Travaglini 2023-04-18 15:51:06 +01:00
  • d55f8f2716 arch: Enable customized decoder class name Roger Chang 2023-09-19 14:31:11 +08:00
  • 5b41112e03 arch-riscv: Make RISC-V decodeInst overridable Roger Chang 2023-09-19 14:12:57 +08:00
  • 391f62b213 misc: 'sim{out/err}' -> 'sim{out/err}.txt' Bobby R. Bruce 2023-08-31 10:26:45 -07:00
  • f5a255c68d configs: Fixed Typo (#337) Bobby R. Bruce 2023-09-21 11:58:49 -07:00
  • 3f9afe96c6 python,util: Add Python MyPy Stubgen to enable Pylance IntelliSense (#307) Bobby R. Bruce 2023-09-21 11:52:16 -07:00
  • d297da3654 cpu: Add override to TraceCPU init function Melissa Jost 2023-09-21 10:11:39 -07:00
  • 7298ebd49b arch-x86: properly initialize the auxv platform string Nicholas Mosier 2023-09-21 05:16:17 +00:00
  • 5697bf26a8 arch-x86: make popx87 micro-op actually pop st(0) Nicholas Mosier 2023-09-21 04:29:05 +00:00
  • 958eda6961 arch-riscv: Fix inst flags for jal and jalr (#325) Bobby R. Bruce 2023-09-20 16:25:21 -07:00
  • aa0702c6eb dev-amdgpu: Handle GPU atomics on host memory addresses (#328) Bobby R. Bruce 2023-09-20 16:24:56 -07:00
  • 4526a314a9 arch-x86: fix negative overflow check bug in PACK micro-op (#332) Bobby R. Bruce 2023-09-20 16:18:16 -07:00
  • 83374bdf99 misc: changed name get_default_disk_device to get_disk_device Leo Redivo 2023-09-20 15:28:49 -07:00
  • 516dcf3bcd configs: Fixed Typo Marco Kurzynski 2023-09-20 21:42:56 +00:00
  • 1fc89bc8ae cpu,mem,dev: Use Addr for cacheLineSize Hoa Nguyen 2023-09-20 14:16:46 -07:00
  • ac5280fedc mem,sim: Change the type of cache_line_size to Addr Hoa Nguyen 2023-09-20 13:49:10 -07:00
  • 3c38d4952a mem: fix bug in 3-level cache Pu (Luke) Yi 2023-09-04 02:16:32 -07:00
  • 63cabf2848 dev-amdgpu: Handle GPU atomics on host memory addresses Matthew Poremba 2023-09-19 13:22:35 -05:00
  • 6eb7c10eb9 misc: Add HACC GPU tests (#258) Bobby R. Bruce 2023-09-20 11:26:54 -07:00
  • 70c1d762c7 arch-riscv: Fix inst flags for jal and jalr Roger Chang 2023-09-18 13:28:12 +08:00
  • 741a901d8d arch-x86: fix negative overflow check bug in PACK micro-op Nicholas Mosier 2023-09-20 05:09:32 +00:00
  • 561f3bd75b misc,tests: Split testlib CI Tests to one dir-per-job Bobby R. Bruce 2023-09-03 23:33:59 -07:00
  • 6921d94373 python: Recursively create checkpoint dir Bobby R. Bruce 2023-09-11 15:25:16 -07:00
  • efd58f9b72 tests: Remove ":" from testing results output dir name Bobby R. Bruce 2023-09-08 10:17:36 -07:00
  • 0337613afc ext,tests: Add --build-targets option to ./main.py list Bobby R. Bruce 2023-09-04 23:34:39 -07:00
  • 13b77b3e41 ext,tests: Allow passing of --uid to ./main.py list Bobby R. Bruce 2023-09-04 15:46:07 -07:00
  • 43226004a1 ext,tests: Fix --figures flag when using ./main.py list Bobby R. Bruce 2023-09-04 15:42:35 -07:00
  • c36a4d12aa tests: Replace print with testlib.log for PARSEC warn Bobby R. Bruce 2023-09-04 22:25:42 -07:00
  • 9057eeabec cpu: Explicitly define cache_line_size -> 64-bit unsigned int Hoa Nguyen 2023-09-19 12:54:18 -07:00