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mem: fix bug in 3-level cache

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Change-Id: I5b875908ac8f81180d781e609869e2f6fe1a8dc4
This commit is contained in:
Pu (Luke) Yi
2023-09-04 02:16:32 -07:00
committed by Bobby R. Bruce
parent 2eeecc532a
commit 3c38d4952a
1 changed files with 3 additions and 3 deletions
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6
src/python/gem5/components/cachehierarchies/ruby/mesi_three_level_cache_hierarchy.py
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@@ -193,10 +193,10 @@ class MESIThreeLevelCacheHierarchy(
if board.has_dma_ports():
dma_ports = board.get_dma_ports()
for i, port in enumerate(dma_ports):
ctrl = DMAController(self.ruby_system.network, cache_line_size)
ctrl.dma_sequencer = DMASequencer(version=i, in_ports=port)
ctrl = DMAController(
DMASequencer(version=i, in_ports=port), self.ruby_system
)
self._dma_controllers.append(ctrl)
ctrl.ruby_system = self.ruby_system
self.ruby_system.num_of_sequencers = len(self._l1_controllers) + len(
self._dma_controllers