From 3c38d4952acde02e88b96d3c8565eeb35561c4c9 Mon Sep 17 00:00:00 2001 From: "Pu (Luke) Yi" Date: Mon, 4 Sep 2023 02:16:32 -0700 Subject: [PATCH] mem: fix bug in 3-level cache Change-Id: I5b875908ac8f81180d781e609869e2f6fe1a8dc4 --- .../ruby/mesi_three_level_cache_hierarchy.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/python/gem5/components/cachehierarchies/ruby/mesi_three_level_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/ruby/mesi_three_level_cache_hierarchy.py index 89b6b21177..3646418572 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/mesi_three_level_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/ruby/mesi_three_level_cache_hierarchy.py @@ -193,10 +193,10 @@ class MESIThreeLevelCacheHierarchy( if board.has_dma_ports(): dma_ports = board.get_dma_ports() for i, port in enumerate(dma_ports): - ctrl = DMAController(self.ruby_system.network, cache_line_size) - ctrl.dma_sequencer = DMASequencer(version=i, in_ports=port) + ctrl = DMAController( + DMASequencer(version=i, in_ports=port), self.ruby_system + ) self._dma_controllers.append(ctrl) - ctrl.ruby_system = self.ruby_system self.ruby_system.num_of_sequencers = len(self._l1_controllers) + len( self._dma_controllers