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arch-riscv: Make RISC-V decodeInst overridable

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The change will allow developers to implement and decode their
non-standard instructions to the CPU models

Bug: 289467440
Test: None
Change-Id: I67f4abc71596f819c1265e325784f51c8e9bb359
This commit is contained in:
Roger Chang
2023-09-19 14:12:57 +08:00
parent f5a255c68d
commit 5b41112e03
1 changed files with 1 additions and 1 deletions
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2
src/arch/riscv/decoder.hh
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@@ -60,7 +60,7 @@ class Decoder : public InstDecoder
ExtMachInst emi;
uint32_t machInst;
StaticInstPtr decodeInst(ExtMachInst mach_inst);
virtual StaticInstPtr decodeInst(ExtMachInst mach_inst);
/// Decode a machine instruction.
/// @param mach_inst The binary instruction to decode.