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arch-arm: Implement FEAT_FGT

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Change-Id: I89391f17f353ab6ce555d65783977c1f30f64fc5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Giacomo Travaglini
2023-04-17 13:44:11 +01:00
parent 37b6824c4c
commit df60b0f5c9
10 changed files with 555 additions and 148 deletions
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14
src/arch/arm/ArmSystem.py
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@@ -1,4 +1,4 @@
# Copyright (c) 2009, 2012-2013, 2015-2022 ARM Limited
# Copyright (c) 2009, 2012-2013, 2015-2023 Arm Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -96,6 +96,8 @@ class ArmExtension(ScopedEnum):
"FEAT_RNG",
"FEAT_RNG_TRAP",
"FEAT_EVT",
# Armv8.6
"FEAT_FGT",
# Armv8.7
"FEAT_HCX",
# Armv9.2
@@ -186,6 +188,8 @@ class ArmDefaultRelease(Armv8):
# Armv8.5
"FEAT_FLAGM2",
"FEAT_EVT",
# Armv8.6
"FEAT_FGT",
# Armv8.7
"FEAT_HCX",
# Armv9.2
@@ -239,8 +243,14 @@ class Armv85(Armv84):
]
class Armv87(Armv85):
class Armv86(Armv85):
extensions = Armv85.extensions + [
"FEAT_FGT",
]
class Armv87(Armv86):
extensions = Armv86.extensions + [
"FEAT_HCX",
]

18
src/arch/arm/isa/insts/branch64.isa
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@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
// Copyright (c) 2011-2013, 2016, 2018, 2020 ARM Limited
// Copyright (c) 2011-2013, 2016, 2018, 2020, 2023 Arm Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -200,11 +200,19 @@ let {{
HtmFailureFaultCause::EXCEPTION);
return fault;
}
Addr newPc;
CPSR cpsr = Cpsr;
CPSR spsr = Spsr;
ExceptionLevel curr_el = currEL(cpsr);
if (fgtEnabled(xc->tcBase()) && curr_el == EL1 &&
static_cast<HFGITR>(xc->tcBase()->readMiscReg(MISCREG_HFGITR_EL2)).eret) {
return std::make_shared<HypervisorTrap>(
machInst, %(trap_iss)d, ExceptionClass::TRAPPED_ERET);
}
switch (curr_el) {
case EL3:
newPc = xc->tcBase()->readMiscReg(MISCREG_ELR_EL3);
@@ -268,7 +276,7 @@ let {{
'''
instFlags = ['IsSerializeAfter', 'IsNonSpeculative', 'IsSquashAfter']
bIop = ArmInstObjParams('eret', 'Eret64', "BranchEret64",
bCode%{'op': ''}, instFlags)
bCode%{'op': '', 'trap_iss' : 0b00}, instFlags)
header_output += BasicDeclare.subst(bIop)
decoder_output += BasicConstructor64.subst(bIop)
exec_output += BasicExecute.subst(bIop)
@@ -278,7 +286,8 @@ let {{
fault = authIA(xc->tcBase(), newPc, XOp1, &newPc);
'''
bIop = ArmInstObjParams('eretaa', 'Eretaa', "BranchEretA64",
bCode % {'op': pac_code} , instFlags)
bCode % {'op': pac_code, 'trap_iss' : 0b10},
instFlags)
header_output += BasicDeclare.subst(bIop)
decoder_output += BasicConstructor64.subst(bIop)
exec_output += BasicExecute.subst(bIop)
@@ -288,7 +297,8 @@ let {{
fault = authIB(xc->tcBase(), newPc, XOp1, &newPc);
'''
bIop = ArmInstObjParams('eretab', 'Eretab', "BranchEretA64",
bCode % {'op': pac_code} , instFlags)
bCode % {'op': pac_code, 'trap_iss' : 0b11},
instFlags)
header_output += BasicDeclare.subst(bIop)
decoder_output += BasicConstructor64.subst(bIop)
exec_output += BasicExecute.subst(bIop)

9
src/arch/arm/isa/insts/misc.isa
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@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
// Copyright (c) 2010-2013,2017-2021 Arm Limited
// Copyright (c) 2010-2013,2017-2021,2023 Arm Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -40,6 +40,13 @@ let {{
svcCode = '''
ThreadContext *tc = xc->tcBase();
if (fgtEnabled(tc) && currEL(tc) == EL0 && !ELIsInHost(tc, EL0) &&
ELIs64(tc, EL1) && static_cast<HFGITR>(
tc->readMiscReg(MISCREG_HFGITR_EL2)).svcEL0) {
return std::make_shared<HypervisorTrap>(
machInst, imm, ExceptionClass::SVC);
}
bool have_semi = ArmSystem::haveSemihosting(tc);
if (have_semi && Thumb && imm == ArmSemihosting::T32Imm) {
// Enable gem5 extensions since we can't distinguish in thumb.

26
src/arch/arm/isa/insts/misc64.isa
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@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
// Copyright (c) 2011-2013, 2016-2018, 2020-2021 Arm Limited
// Copyright (c) 2011-2013, 2016-2018, 2020-2021, 2023 Arm Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -43,7 +43,29 @@ let {{
HtmFailureFaultCause::EXCEPTION);
return fault;
}
fault = std::make_shared<SupervisorCall>(machInst, bits(machInst, 20, 5));
const uint32_t iss = bits(machInst, 20, 5);
if (fgtEnabled(xc->tcBase())) {
ExceptionLevel curr_el = currEL(xc->tcBase());
HFGITR hfgitr = xc->tcBase()->readMiscReg(MISCREG_HFGITR_EL2);
switch (curr_el) {
case EL0:
if (!ELIsInHost(xc->tcBase(), curr_el) && hfgitr.svcEL0) {
return std::make_shared<HypervisorTrap>(
machInst, iss, ExceptionClass::SVC_64);
}
break;
case EL1:
if (hfgitr.svcEL1) {
return std::make_shared<HypervisorTrap>(
machInst, iss, ExceptionClass::SVC_64);
}
break;
default:
break;
}
}
fault = std::make_shared<SupervisorCall>(machInst, iss);
'''
svcIop = ArmInstObjParams("svc", "Svc64", "ImmOp64",

490
src/arch/arm/regs/misc.cc
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File diff suppressed because it is too large Load Diff

15
src/arch/arm/regs/misc.hh
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@@ -1096,6 +1096,11 @@ namespace ArmISA
MISCREG_RNDR,
MISCREG_RNDRRS,
// FEAT_FGT
MISCREG_HFGITR_EL2,
MISCREG_HFGRTR_EL2,
MISCREG_HFGWTR_EL2,
// NUM_PHYS_MISCREGS specifies the number of actual physical
// registers, not considering the following pseudo-registers
// (dummy registers), like MISCREG_UNKNOWN, MISCREG_IMPDEF_UNIMPL.
@@ -1126,10 +1131,6 @@ namespace ArmISA
MISCREG_VSESR_EL2,
MISCREG_VDISR_EL2,
// FGT extension (unimplemented)
MISCREG_HFGRTR_EL2,
MISCREG_HFGWTR_EL2,
// PSTATE
MISCREG_PAN,
MISCREG_UAO,
@@ -2766,6 +2767,10 @@ namespace ArmISA
"rndr",
"rndrrs",
"hfgitr_el2",
"hfgrtr_el2",
"hfgwtr_el2",
"num_phys_regs",
// Dummy registers
@@ -2784,8 +2789,6 @@ namespace ArmISA
"disr_el1",
"vsesr_el2",
"vdisr_el2",
"hfgrtr_el2",
"hfgwtr_el2",
// PSTATE
"pan",

114
src/arch/arm/regs/misc_types.hh
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010-2022 Arm Limited
* Copyright (c) 2010-2023 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -363,6 +363,7 @@ namespace ArmISA
BitUnion64(SCR)
Bitfield<40> trndr;
Bitfield<38> hxen;
Bitfield<27> fgten;
Bitfield<21> fien;
Bitfield<20> nmea;
Bitfield<19> ease;
@@ -931,6 +932,117 @@ namespace ArmISA
Bitfield<3,0> pcsample;
EndBitUnion(DEVID)
BitUnion64(HFGITR)
Bitfield<54> dccvac;
Bitfield<53> svcEL1;
Bitfield<52> svcEL0;
Bitfield<51> eret;
Bitfield<47> tlbivaale1;
Bitfield<46> tlbivale1;
Bitfield<45> tlbivaae1;
Bitfield<44> tlbiaside1;
Bitfield<43> tlbivae1;
Bitfield<42> tlbivmalle1;
Bitfield<41> tlbirvaale1;
Bitfield<40> tlbirvale1;
Bitfield<39> tlbirvaae1;
Bitfield<38> tlbirvae1;
Bitfield<37> tlbirvaale1is;
Bitfield<36> tlbirvale1is;
Bitfield<35> tlbirvaae1is;
Bitfield<34> tlbirvae1is;
Bitfield<33> tlbivaale1is;
Bitfield<32> tlbivale1is;
Bitfield<31> tlbivaae1is;
Bitfield<30> tlbiaside1is;
Bitfield<29> tlbivae1is;
Bitfield<28> tlbivmalle1is;
Bitfield<27> tlbirvaale1os;
Bitfield<26> tlbirvale1os;
Bitfield<25> tlbirvaae1os;
Bitfield<24> tlbirvae1os;
Bitfield<23> tlbivaale1os;
Bitfield<22> tlbivale1os;
Bitfield<21> tlbivaae1os;
Bitfield<20> tlbiaside1os;
Bitfield<19> tlbivae1os;
Bitfield<18> tlbivmalle1os;
Bitfield<17> ats1e1wp;
Bitfield<16> ats1e1rp;
Bitfield<15> ats1e0w;
Bitfield<14> ats1e0r;
Bitfield<13> ats1e1w;
Bitfield<12> ats1e1r;
Bitfield<11> dczva;
Bitfield<10> dccivac;
Bitfield<9> dccvapd;
Bitfield<8> dccvap;
Bitfield<7> dccvau;
Bitfield<6> dccisw;
Bitfield<5> dccsw;
Bitfield<4> dcisw;
Bitfield<3> dcivac;
Bitfield<2> icivau;
Bitfield<1> iciallu;
Bitfield<0> icialluis;
EndBitUnion(HFGITR)
// HFGRTR and HFGWTR. Some fields are
// for HFGRTR only (RO registers)
BitUnion64(HFGTR)
Bitfield<50> nAccdataEL1;
Bitfield<49> erxaddrEL1;
Bitfield<48> erxpfgcdnEL1;
Bitfield<47> erxpfgctlEL1;
Bitfield<46> erxpfgfEL1; // RES0 for HFGWTR
Bitfield<45> erxmiscNEL1;
Bitfield<44> erxstatusEL1;
Bitfield<43> erxctlrEL1;
Bitfield<42> erxfrEL1;
Bitfield<41> errselrEL1;
Bitfield<40> erridrEL1; // RES0 for HFGWTR
Bitfield<39> iccIgrpEnEL1;
Bitfield<38> vbarEL1;
Bitfield<37> ttbr1EL1;
Bitfield<36> ttbr0EL1;
Bitfield<35> tpidrEL0;
Bitfield<34> tpidrroEL0;
Bitfield<33> tpidrEL1;
Bitfield<32> tcrEL1;
Bitfield<31> scxtnumEL0;
Bitfield<30> scxtnumEL1;
Bitfield<29> sctlrEL1;
Bitfield<28> revidrEL1; // RES0 for HFGWTR
Bitfield<27> parEL1;
Bitfield<26> mpidrEL1; // RES0 for HFGWTR
Bitfield<25> midrEL1; // RES0 for HFGWTR
Bitfield<24> mairEL1;
Bitfield<23> lorsaEL1;
Bitfield<22> lornEL1;
Bitfield<21> loridEL1; // RES0 for HFGWTR
Bitfield<20> loreaEL1;
Bitfield<19> lorcEL1;
Bitfield<18> isrEL1; // RES0 for HFGWTR
Bitfield<17> farEL1;
Bitfield<16> esrEL1;
Bitfield<15> dczidEL0; // RES0 for HFGWTR
Bitfield<14> ctrEL0; // RES0 for HFGWTR
Bitfield<13> csselrEL1;
Bitfield<12> cpacrEL1;
Bitfield<11> contextidrEL1;
Bitfield<10> clidrEL1; // RES0 for HFGWTR
Bitfield<9> ccsidrEL1; // RES0 for HFGWTR
Bitfield<8> apibKey;
Bitfield<7> apiaKey;
Bitfield<6> apgaKey;
Bitfield<5> apdbKey;
Bitfield<4> apdaKey;
Bitfield<3> amairEL1;
Bitfield<2> aidrEL1; // RES0 for HFGWTR
Bitfield<1> afsr1EL1;
Bitfield<0> afsr0EL1;
EndBitUnion(HFGTR)
} // namespace ArmISA
} // namespace gem5

3
src/arch/arm/types.hh
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010, 2012-2013, 2017-2018, 2022 Arm Limited
* Copyright (c) 2010, 2012-2013, 2017-2018, 2022-2023 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -323,6 +323,7 @@ namespace ArmISA
SMC_64 = 0x17,
TRAPPED_MSR_MRS_64 = 0x18,
TRAPPED_SVE = 0x19,
TRAPPED_ERET = 0x1A,
TRAPPED_SME = 0x1D,
PREFETCH_ABORT_TO_HYP = 0x20,
PREFETCH_ABORT_LOWER_EL = 0x20, // AArch64 alias

10
src/arch/arm/utility.cc
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2009-2014, 2016-2020, 2022 Arm Limited
* Copyright (c) 2009-2014, 2016-2020, 2022-2023 Arm Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -1347,5 +1347,13 @@ syncVecElemsToRegs(ThreadContext *tc)
}
}
bool
fgtEnabled(ThreadContext *tc)
{
return EL2Enabled(tc) && HaveExt(tc, ArmExtension::FEAT_FGT) &&
(!ArmSystem::haveEL(tc, EL3) ||
static_cast<SCR>(tc->readMiscReg(MISCREG_SCR_EL3)).fgten);
}
} // namespace ArmISA
} // namespace gem5

4
src/arch/arm/utility.hh
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010, 2012-2013, 2016-2020, 2022 Arm Limited
* Copyright (c) 2010, 2012-2013, 2016-2020, 2022-2023 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -364,6 +364,8 @@ bool isUnpriviledgeAccess(ThreadContext *tc);
void syncVecRegsToElems(ThreadContext *tc);
void syncVecElemsToRegs(ThreadContext *tc);
bool fgtEnabled(ThreadContext *tc);
} // namespace ArmISA
} // namespace gem5