dev,arch-riscv: Mark gem5's 8250 UART as 16550a compatible

8250 UART is supposed to be compatible to 16550a UART.

This enables OpenSBI to print things to UART as OpenSBI only
prints if the UART is 16550a compatible [1].

There is a similar change from gem5 gerrit [2] pointing out
that this also enables bbl to print things to UART. This is
confirmed :)

[1] https://github.com/riscv-software-src/opensbi/blob/v1.3.1/lib/utils/serial/fdt_serial_uart8250.c#L29
[2] https://gem5-review.googlesource.com/c/public/gem5/+/68481

Signed-off-by: Hoa Nguyen <hn@hnpl.org>

src/dev/serial/Uart.py

@@ -82,5 +82,5 @@ class RiscvUart8250(Uart8250):
         node.append(FdtPropertyWords("interrupts", [platform.uart_int_id]))
         node.append(FdtPropertyWords("clock-frequency", [0x384000]))
         node.append(FdtPropertyWords("interrupt-parent", state.phandle(plic)))
-        node.appendCompatible(["ns8250"])
+        node.appendCompatible(["ns8250", "ns16550a"])
         yield node

src/python/gem5/components/boards/riscv_board.py

@@ -438,7 +438,7 @@ class RiscvBoard(AbstractSystemBoard, KernelDiskWorkload):
         uart_node.append(
             FdtPropertyWords("interrupt-parent", soc_state.phandle(plic))
         )
-        uart_node.appendCompatible(["ns8250"])
+        uart_node.appendCompatible(["ns8250", "ns16550a"])
         soc_node.append(uart_node)
 
         # VirtIO MMIO disk node