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arch-riscv: Add all supporting Z extensions to RISC-V isa string

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Change-Id: I809744fc546bc5c0e27380f9b75bdf99f8520583
Signed-off-by: Hoa Nguyen <hn@hnpl.org>
This commit is contained in:
Hoa Nguyen
2023-10-30 02:36:24 +00:00
parent f615ee4cd4
commit 7c6fcb3838
1 changed files with 11 additions and 0 deletions
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11
src/arch/riscv/RiscvISA.py
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@@ -109,4 +109,15 @@ class RiscvISA(BaseISA):
if self.enable_rvv.value == True:
isa_extensions.append("v")
isa_string = "".join(isa_extensions)
isa_string += "_Zicbom" # Cache-block Management Instructions
isa_string += "_Zicboz" # Cache-block Zero Instruction
isa_string += "_Zicntr" # Performance Couter Spec
isa_string += "_Zicsr" # RMW CSR Instructions (Privileged Spec)
isa_string += "_Zifencei" # FENCE.I Instruction (Unprivileged Spec)
isa_string += "_Zihpm" # Performance Couter Spec
isa_string += "_Zba" # Address Generation
isa_string += "_Zbb" # Basic Bit Manipulation
isa_string += "_Zbs" # Single-bit Instructions
return isa_string