From 7c6fcb38386cce2121e699e2eab75e01ea98d97d Mon Sep 17 00:00:00 2001 From: Hoa Nguyen Date: Mon, 30 Oct 2023 02:36:24 +0000 Subject: [PATCH] arch-riscv: Add all supporting Z extensions to RISC-V isa string Change-Id: I809744fc546bc5c0e27380f9b75bdf99f8520583 Signed-off-by: Hoa Nguyen --- src/arch/riscv/RiscvISA.py | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/arch/riscv/RiscvISA.py b/src/arch/riscv/RiscvISA.py index 62dcffb5d8..ca533bef0e 100644 --- a/src/arch/riscv/RiscvISA.py +++ b/src/arch/riscv/RiscvISA.py @@ -109,4 +109,15 @@ class RiscvISA(BaseISA): if self.enable_rvv.value == True: isa_extensions.append("v") isa_string = "".join(isa_extensions) + + isa_string += "_Zicbom" # Cache-block Management Instructions + isa_string += "_Zicboz" # Cache-block Zero Instruction + isa_string += "_Zicntr" # Performance Couter Spec + isa_string += "_Zicsr" # RMW CSR Instructions (Privileged Spec) + isa_string += "_Zifencei" # FENCE.I Instruction (Unprivileged Spec) + isa_string += "_Zihpm" # Performance Couter Spec + isa_string += "_Zba" # Address Generation + isa_string += "_Zbb" # Basic Bit Manipulation + isa_string += "_Zbs" # Single-bit Instructions + return isa_string