arch-riscv: Define VecRegContainer with maximum expected length

This path redefine VecRegContainer for RISCV so it can hold every VLEN + ELEN possible configuration used at execution time

Change-Id: Ie6abd01a1c4ebe9aae3d93f4e835fcfdc4a82dcd

src/arch/riscv/regs/vector.hh

@@ -36,6 +36,7 @@
 
 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
+#include "arch/riscv/types.hh"
 #include "base/bitunion.hh"
 #include "cpu/reg_class.hh"
 #include "debug/VecRegs.hh"
@@ -46,13 +47,10 @@ namespace gem5
 namespace RiscvISA
 {
 
-constexpr unsigned ELEN = 64;
-constexpr unsigned VLEN = 256;
-constexpr unsigned VLENB = VLEN / 8;
-
-using VecRegContainer = gem5::VecRegContainer<VLENB>;
+using VecRegContainer = gem5::VecRegContainer<MaxVecLenInBytes>;
 using vreg_t = VecRegContainer;
 
+
 const int NumVecStandardRegs = 32;
 const int NumVecInternalRegs = 8; // Used by vector uop
 const int NumVecRegs = NumVecStandardRegs + NumVecInternalRegs;

src/arch/riscv/types.hh

@@ -178,6 +178,10 @@ BitUnion64(ExtMachInst)
 
 EndBitUnion(ExtMachInst)
 
+constexpr unsigned MaxVecLenInBits = 65536;
+constexpr unsigned MaxVecLenInBytes  = MaxVecLenInBits >> 3;
+
+
 } // namespace RiscvISA
 } // namespace gem5