arch-riscv: Add vlen component to decoder state

This patch add vlen definition to the riscv decoder so it can be used in Vector Instruction Constructors

Change-Id: I52292bc261c43562b690062b16d2b323675c2fe0

src/arch/riscv/decoder.cc

@@ -41,6 +41,8 @@ namespace RiscvISA
 
 Decoder::Decoder(const RiscvDecoderParams &p) : InstDecoder(p, &machInst)
 {
+    ISA *isa = dynamic_cast<ISA*>(p.isa);
+    vlen = isa->getVecLenInBits();
     reset();
 }
 

src/arch/riscv/decoder.hh

@@ -60,6 +60,8 @@ class Decoder : public InstDecoder
     ExtMachInst emi;
     uint32_t machInst;
 
+    uint32_t vlen;
+
     virtual StaticInstPtr decodeInst(ExtMachInst mach_inst);
 
     /// Decode a machine instruction.