From 8a20f20f791a316c5543af2e5c45bcca94bc3667 Mon Sep 17 00:00:00 2001
From: Alvaro Moreno <alvaro.moreno@bsc.es>
Date: Thu, 14 Sep 2023 09:43:43 +0200
Subject: [PATCH] arch-riscv: Add vlen component to decoder state

This patch add vlen definition to the riscv decoder so it can be used in Vector Instruction Constructors

Change-Id: I52292bc261c43562b690062b16d2b323675c2fe0
---
 src/arch/riscv/decoder.cc | 2 ++
 src/arch/riscv/decoder.hh | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/src/arch/riscv/decoder.cc b/src/arch/riscv/decoder.cc
index b1e2948e93..3c199b3210 100644
--- a/src/arch/riscv/decoder.cc
+++ b/src/arch/riscv/decoder.cc
@@ -41,6 +41,8 @@ namespace RiscvISA
 
 Decoder::Decoder(const RiscvDecoderParams &p) : InstDecoder(p, &machInst)
 {
+    ISA *isa = dynamic_cast<ISA*>(p.isa);
+    vlen = isa->getVecLenInBits();
     reset();
 }
 
diff --git a/src/arch/riscv/decoder.hh b/src/arch/riscv/decoder.hh
index c827e85f90..b53c48445d 100644
--- a/src/arch/riscv/decoder.hh
+++ b/src/arch/riscv/decoder.hh
@@ -60,6 +60,8 @@ class Decoder : public InstDecoder
     ExtMachInst emi;
     uint32_t machInst;
 
+    uint32_t vlen;
+
     virtual StaticInstPtr decodeInst(ExtMachInst mach_inst);
 
     /// Decode a machine instruction.