diff --git a/src/arch/riscv/decoder.cc b/src/arch/riscv/decoder.cc
index b1e2948e93..3c199b3210 100644
--- a/src/arch/riscv/decoder.cc
+++ b/src/arch/riscv/decoder.cc
@@ -41,6 +41,8 @@ namespace RiscvISA
 
 Decoder::Decoder(const RiscvDecoderParams &p) : InstDecoder(p, &machInst)
 {
+    ISA *isa = dynamic_cast<ISA*>(p.isa);
+    vlen = isa->getVecLenInBits();
     reset();
 }
 
diff --git a/src/arch/riscv/decoder.hh b/src/arch/riscv/decoder.hh
index c827e85f90..b53c48445d 100644
--- a/src/arch/riscv/decoder.hh
+++ b/src/arch/riscv/decoder.hh
@@ -60,6 +60,8 @@ class Decoder : public InstDecoder
     ExtMachInst emi;
     uint32_t machInst;
 
+    uint32_t vlen;
+
     virtual StaticInstPtr decodeInst(ExtMachInst mach_inst);
 
     /// Decode a machine instruction.