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901 Commits

Author SHA1 Message Date
Gabe Black
fa877e19d3 arm: Get rid of using namespace std and TheISA in realview.cc. 
Neither was actually used by the nearly empty file.

Change-Id: Ief1b77b18c8c616511bf9870e1667439a42dfcbd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22266
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-10-30 00:42:07 +00:00
Gabe Black
dd3abb296f dev: Remove SINIC_VTOPHYS and related code. 
The code in this #ifdef isn't turned on by anything, and either has or
likely will bitrot, especially since there are no tests to even
determine manually if the code they guard works. They are also
preceeded by panics which say that the code they guard is known not to
work now anyway.

This change also gets rid of TheISA in that file since the only reason
it was around was for vtophys in the guarded code.

Change-Id: I59fd8974d0dd3d7ab0d5a8ccfa6a446d2da41eb0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22265
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-10-30 00:42:07 +00:00
Gabe Black
1d5119e891 alpha: Remove TheISA from the Alpha devices. 
These are the from the various bits of the tsunami platform. They
primarily consisted of "using TheISA" which could be replaced with
using AlphaISA or removed altogether (I went with the later), and use
of TheISA:: which I replaced with AlphaISA::.

Change-Id: Ic52577c65241a92a3f1ae318a19431f8faa50a66
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22264
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-10-30 00:42:07 +00:00
Gabe Black
e7ab65eab2 x86: Remove TheISA from x86 devices. 
This was really only in the PC platform class.

Change-Id: I5365d965ea335a7c45be9f80706a875b19ed0417
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22263
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-10-30 00:23:36 +00:00
Giacomo Travaglini
e77b9d0424 configs: Clean setupBootLoader signature 
This is because the bus parameter is not used anymore

Change-Id: I27aa8cc064904a6e3e0376f61eb7db74ea1a4d6c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22002
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
 2019-10-22 13:09:47 +00:00
Giacomo Travaglini
8e36db16ce dev-arm, configs: Using _on_chip_memory for on chip memory 
This patch is pulling the on-chip memory outside of the on_chip_devices
list.
The external interface will be more or less the same: configuration
scripts will still use the attachOnChipIO method; a new kw argument has
been added in order to store mem_ports.

We want to provide to on-chip memory the same mechanism used when
collecting on-chip dma ports. This is needed when using Ruby, since
we need to pass a non None mem_ports to prevent the bootmem to be
wired to the bus.

Change-Id: Ifc519c3072dc5de1530772c70c80dc2094e2c54c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22000
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-10-22 10:24:54 +00:00
Gabe Black
ae390c629f arch: Make a base class for Interrupts. 
That abstracts the ISA further from the CPU, getting us a small step
closer to being able to build in more than one ISA at a time.

Change-Id: Ibf7e26a3df411ffe994ac1e11d2a53b656863223
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20831
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-10-19 01:45:48 +00:00
Tiago Muck
1c047f8b92 dev-arm: Check for gem5 extensions in GicV2 
Using GicV2 without setting the gem5_extensions parameter in a
config  with more than 8 is not allowed to prevent overflow of
the 8-bit mask.

Change-Id: I780c6985e8f44ed780b4f74f9a27805124e23a7b
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19288
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-10-18 22:44:26 +00:00
Gabe Black
245422102c x86: Use a std::function to handle MSI completion. 
This removes the recvResponse callback from the IntMasterPort, and
makes it easier to handle the default case where we just need to clean
up the Packet.

Change-Id: I8bcbfee0aaf68b12310d773f925c399fc87ea65d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20828
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
 2019-10-15 22:46:31 +00:00
Giacomo Travaglini
008ae4b065 dev-arm: Carve out a portion of VExpress_GEM5 for the bootloader 
This patch is carving out a portion of VExpress_GEM5 memory for the
bootloader. Prior to this patch this was only happening
conditionally/dynamically via the setupBootLoader call.  With this patch
the region is always present and the setupBootLoader doesn't instantiate
memory, it is only setting up some bootloader parameters.

Change-Id: Iaa5cdf471b14e8faa37353a25631bf7c6fc64afc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21604
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-10-15 08:33:09 +00:00
Gabe Black
3b58400b27 x86: De-x86ify the IntMasterPort. 
The devices which host an IntMasterPort are very specific to x86 at the
moment, but the ports don't have to be. This change moves
responsibilities around so that the x86 specific aspects are handled
in the device, and the ports themselves are ISA agnostic.

Change-Id: I50141b66895be7d8f6303605505002ef424af7fd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20827
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-10-15 00:47:23 +00:00
Gabe Black
6ad5f1516e x86: Simplify and consolidate the code that assembles an MSI on x86. 
There is no interrupt response message, and so no need for a function
which would construct one. The other functions which construct the
request can be consolidated since the work being done by each is
incremental. The template parameters can be used to support multiple
types and offsets in a single function, and since that function also
doesn't have to do much work, it makes sense to do everything in one
shot.

Change-Id: I41b202a263a697c5ada6817f3ab2a4728281b894
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20826
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
 2019-10-14 21:16:06 +00:00
Gabe Black
75b19403a7 x86: Stop using and delete the x86 IntDevice class. 
Most of its functionality has been exported already. This change makes
the two classes which were inheriting IntDevice create an IntMasterPort
themselves.

Change-Id: I73d17cd79cf8252b0e26dd2576f552bf9054adf4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20825
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-10-12 04:11:57 +00:00
Giacomo Travaglini
e5914503f7 dev-arm, configs: Remove RealViewPBX platform 
This is an old unused platform. We should support VExpress_GEM5 based
platforms only.

Change-Id: If9c29047b2d068992dfbbe0dc268c70b788cce5f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21601
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-10-10 14:05:30 +00:00
Bobby R. Bruce
432afa21f5 dev, misc: Fixing "may be used unitialized" compilation error 
When compiling using "scons build/X86/base", "error: 'tx_queue_size'
may be used uninitialized in this function" is received (cc1plus:
all warnings treated as errors). tx_queue_size is now initialized
to zero to avoid this compilation error.

Change-Id: I0e2a4fd9ad6053c4c4124c83da9a7919778bcc52
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21399
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-10-03 21:11:08 +00:00
Marc Mari Barcelo
2e98297d62 dev-arm: Improve fault message on SMMUv3 translation fault 
Change-Id: Ib1d7ae73951b52f2378f8bd50e804d3237f74074
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21303
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-10-02 15:55:06 +00:00
Marc Mari Barcelo
ee4648fa7e dev-arm: Fix address used to update the SMMUv3 Walk Cache 
Last level of SMMUv3 WalkCache should store the address without an offset.

Change-Id: I1046bd8210500c2c38802acd41a4403e52fd3c90
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21302
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-10-02 15:55:06 +00:00
Gabe Black
f89f85d255 x86: Switch from MessageReq and Resp to WriteReq and Resp. 
Originally MessageReq was intended to mark a packet as a holding a
message destined for a particular recipient and which would not
interact with other packets.

This is similar to the way a WriteReq would behave if writing to a
device register which needs to be updated atomically. Also, while the
memory system *could* recognize a MessageReq and know that it didn't
need to interact with other packets, that was never implemented.

Change-Id: Ie54301d1d8820e206d6bae96e200ae8c71d2d784
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20823
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
 2019-10-02 01:28:32 +00:00
Gabe Black
e6c6f0601c x86: Templatize the IntMasterPort. 
This makes the IntMasterPort usable with any class, making it possible
to avoid inheriting from IntDevice.

It also makes IntMasterPort inherit directly from QueuedMasterPort,
skipping over MessageMasterPort.

Change-Id: I9d218556c838ea567ced5f6fa4d57a3ec9d28d31
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20821
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
 2019-09-21 05:05:18 +00:00
Gabe Black
cc03cf8270 x86: Templatize IntSlavePort. 
This makes the device IntSlavePort calls back into based on a template
parameter so that IntDevice doesn't have to be in the inheritance
hierarchy to use it.

It also makes IntSlavePort inherit from SimpleTimingPort directly,
skipping over MessageSlavePort.

Change-Id: Ic3213edc9c3ed5e506ee1e9f5e082cd47d7c7998
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20820
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
 2019-09-21 05:05:18 +00:00
Gabe Black
679ed0eec5 dev, x86: Delete the now unused X86 specific interrupt pins/lines. 
Change-Id: I3915f0ad673119b551dcc4c5cedec180a9b88735
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20702
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-20 17:55:13 +00:00
Gabe Black
ab376064bd dev, x86: Convert x86 devices to the generic int pins. 
Change-Id: I4551ad00cf205c31555c90b53e87bc206a8d8729
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20701
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-20 17:54:39 +00:00
Andrea Mondelli
dc2db5cf9b dev: Terminal output's dump name conflicts 
The recently Terminal dump options name introduced
in patch 1c72e90 conflict with MacOS stdio.h header.

From stdio.h:

#define	stdin	__stdinp
#define	stdout	__stdoutp
#define	stderr	__stderrp

To remove this conflict, the TerminalDump options are renamed.

Change-Id: I1b60fa1031328fc32d6a58bf7889b6e479d95219
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20959
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-19 21:46:32 +00:00
Giacomo Travaglini
f525028c12 dev-arm: Conditionally enable HDLcd when doing DTB autogen 
This is a preparation change for a real DTB autogen implementation

Change-Id: Ia0c1c5e65ea96036e55455eb4222cec12944d33a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20331
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-19 15:49:27 +00:00
Giacomo Travaglini
2e55ff352f dev-arm: Add HDLcd DTB autogeneration 
A Display has been defined. Its sole purpose is to generate the device
tree node to be referenced by the HDLcd device.  The encoder parameters
are based on the existing node defined in:

system/arm/dt/armv8.dts

Change-Id: I6cdeb0437dce207dbd0f2c65c16b224245eb74e1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20330
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-19 15:49:27 +00:00
Giacomo Travaglini
59aed6f3bd dev-arm: Allow IOMMU binding to HDLcd 
Change-Id: I894080e7bd76e7efedef141c937e1561c0c0527c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20841
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-16 09:10:43 +00:00
Giacomo Travaglini
587c94c773 dev-arm: Store the IOMMU reference from within the SMMU::connect 
Change-Id: I35718a71dc040ee4acad9eee2a07076ebb571304
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20840
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-13 08:14:24 +00:00
Giacomo Travaglini
3d494d763d dev: Enable DTB IOMMU binding with a DMA object 
This happens by storing a iommu reference in the dma device, and by
calling the addIommuProperty method once doing dtb autogeneration for
the device

Change-Id: Ibd585addac686a9eeaba6959f459d81901087549
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20839
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-13 08:14:24 +00:00
Gabe Black
c9fabe1179 dev: Generalize the x86 int source/sink pins. 
Sink pins are now templated based on the underlying device types, and
the pins themselves are based on the new, generalized Port mechanism.

Change-Id: I09c678c56f6eb6b4a167c12f221ae0241fe99c2d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20700
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-12 20:36:39 +00:00
Giacomo Travaglini
a04da61ce1 dev-arm: Reset HPPI when clearing an LPI 
Change-Id: I2a69e6cef69aa48d7c265d59915b859e5eac2bcc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20638
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-09 08:48:30 +00:00
Giacomo Travaglini
bd2d851548 dev-arm: Add resetHppi method in the GICv3 cpu interface 
The method is used for resetting the highest priority pending interrupt
interrupt from the cpu interface if it matches the intid passed as an
argument.

Change-Id: I9fbc4cb3e05a1cc32f853b6afab5c2bc99369435
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20637
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-09 08:48:30 +00:00
Giacomo Travaglini
8ea1bd8ad0 dev-arm: Cleanup GICv3 initialization 
This patch is removing the unnecessary initState() / reset() methods
from GICv3 classes, since we can initialize everything at
construction/init time

Change-Id: Ia70edcc4ca4f11878fac0024342e4f2cd81883a0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20636
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-09 08:48:30 +00:00
Giacomo Travaglini
e5e1d85bbb dev-arm: Initialize GICD_TYPER once at construction time 
Change-Id: Ib4dfdf7005709c22b4ba95099b1192f6edd6ff06
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20635
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-09 08:48:30 +00:00
Giacomo Travaglini
0004a6a060 dev-arm: Writes to IGRPEN1_EL3 triggering update 
Change-Id: I56804eb1bfc8913bd0d3cab05865a382bf270bc1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20634
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-09 08:48:30 +00:00
Giacomo Travaglini
59370dde2e dev-arm: Fix GICv3 ITS cmdq wrapping 
Change-Id: I979e8d1378d5b5d2647158798479cf4238f2c349
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20633
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-09 08:48:30 +00:00
Giacomo Travaglini
54e6625546 dev-arm: Fix mapping between IGRPEN1_EL3 and IGRPEN1_EL1 
Previous mapping was wrong because it was checking which security bits
it was accessing by using the inSecureState() function, whereas it
should have used the isSecureBelowEL3().  This patch is not making the
sostitution since it is optimizing the mapping furthermore by avoiding
updating both IGRPEN1_EL1 and  IGRPEN1_EL3 on writes.  The IGRPEN1_EL1
register is used as a storage, and any reads/writes to IGRPEN1_EL3 is
routed to that register.

Change-Id: Id318ec44e19d4f844e4e3410d74d0c4f89810811
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20632
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-09 08:48:30 +00:00
Giacomo Travaglini
5aa85f38cb dev-arm: Implement message-based SPIs 
Change-Id: I35e79dfd572c3e0d9cadc8e0aab01befd6004ece
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20631
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-09 08:48:30 +00:00
Gabe Black
37551510ea dev: Scrub out some lingering uses of MemObject. 
MemObject doesn't do anything any more, and is basically just an alias
for ClockedObject.

Change-Id: Ic0e1658609e4e1d7f4b829fbc421f222e4869dee
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20719
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-09 01:54:36 +00:00
Giacomo Travaglini
286b6267af dev-arm: Add GICD_SGIR register 
The Distributor Software Generated Interrupt Register is implemented
only if affinity routing is disabled. Since this configuration is
currently not supported in gem5, it has to be treated as RES0.

Change-Id: I9ffcb31b26fc17547f74a4f1d43ce72c59786fa8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20630
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-07 12:12:55 +00:00
Giacomo Travaglini
1c72e90e4e dev: Enable Terminal output's dump to stdout 
While the default option is to dump the Terminal content in a file (e.g.
m5out/system.terminal), with this patch it will be possible to choose to
dump it to standard output.

Change-Id: If51c2fd671fa3eb0867a855b5f7d3b0df9cad025
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20639
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-09-06 20:01:25 +00:00
Giacomo Travaglini
e7c75d2c11 dev-arm: State update when setting MISCREG_ICC_IGRPENx register 
This is because by enabling ainterrupt group at the cpu interface, we
need to check if a previously pending interrupt needs to be forwarded to
the PE.
We are doing the same when globally enabling irqs in the distributor
(GICD_CTLR).

Change-Id: I80aeb87b2a58a108de899006d5a2f12eadbe6c2e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20629
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 20:00:34 +00:00
Giacomo Travaglini
2a818db77a arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64 banking 
Change-Id: Ic08ac1e7f3ebef408a83aa068ce15e9dfe2aa3cd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20628
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 20:00:34 +00:00
Giacomo Travaglini
34f1b771ed arch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64 banking 
Change-Id: Ide93464f62288fbe8f409f718487a15512c01295
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20627
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 20:00:34 +00:00
Giacomo Travaglini
22273000d0 arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 banking 
Change-Id: Ib1691f1cba08251a36ceb959849b61c33cc3e93b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20626
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 20:00:34 +00:00
Giacomo Travaglini
96fdb20871 dev-arm: Add read/writeBanked helpers to GICv3 
These will be used by AA64 security banked registers in GICv3.

Change-Id: Ia980c4f5c14187ab9c18da1d1d596562644111ae
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20624
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 20:00:34 +00:00
Chun-Chen TK Hsu
665b67e365 dev: Fix segmentation fault in VirtIOBlock 
GEM5 got a segmentation fault when the size is large in
VirtIOBlock::write. This change uses a vector to avoid this segmentation
fault.

Signed-off-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Change-Id: I26272686a6e7e39cdf2389657ecd38ce90261144
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20679
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 16:14:30 +00:00
Giacomo Travaglini
ead1e7a2a3 dev-arm: Rewrite ICC_BPR0/ICC_BPR1 handling 
The patch is fixing BPR reads in AA32, by removing the line

Gicv3::GroupId group =
    misc_reg == MISCREG_ICC_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1S;

Where a read to ICC_BPR0 will return a G1S group.
The patch is also fixing Security banking accesses.

Change-Id: I28f1d1244c44d4b8b202d3141f8380943c7c1c86
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20620
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 11:53:49 +00:00
Giacomo Travaglini
51022bfe0e dev-arm: Add GICv3 unimplemented Hyp Active Priorities Group regs 
ICH_APxR1, ICH_APxR2, ICH_APxR3 are implemented only if supporting more
than 6 bits of priority. Since this is not the case, they are currently
unimplemented.
According to spec, unimplemented registers are RAZ/WI.

Change-Id: Ifd7f7a3d42b4575c2f7aff3b95d5a47ac1e61842
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20619
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 11:53:49 +00:00
Giacomo Travaglini
7a1f018ce7 dev-arm: Allow 32-bit access to GITS_TYPER 
Change-Id: I9d19174b38ba70f82050102f955ccc162965d1fb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20618
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 11:53:49 +00:00
Giacomo Travaglini
7f89594029 dev-arm: Cpu interface groupEnabled check for global enable 
Gicv3CPUInterface::groupEnabled should check for global enable flags at
distributor level:
- Gicv3Distributor.EnableGrp0
- Gicv3Distributor.EnableGrp1S
- Gicv3Distributor.EnableGrp1NS

Change-Id: I1c855b0e4c2bc8f1cd0a8f086b9450f516177b08
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20617
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-09-06 11:53:49 +00:00