x86: Switch from MessageReq and Resp to WriteReq and Resp.
Originally MessageReq was intended to mark a packet as a holding a message destined for a particular recipient and which would not interact with other packets. This is similar to the way a WriteReq would behave if writing to a device register which needs to be updated atomically. Also, while the memory system *could* recognize a MessageReq and know that it didn't need to interact with other packets, that was never implemented. Change-Id: Ie54301d1d8820e206d6bae96e200ae8c71d2d784 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20823 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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@@ -307,7 +307,7 @@ Tick
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X86ISA::Interrupts::recvMessage(PacketPtr pkt)
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{
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Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0);
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assert(pkt->cmd == MemCmd::MessageReq);
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assert(pkt->cmd == MemCmd::WriteReq);
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switch(offset)
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{
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case 0:
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@@ -335,7 +335,7 @@ bool
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X86ISA::Interrupts::recvResponse(PacketPtr pkt)
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{
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assert(!pkt->isError());
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assert(pkt->cmd == MemCmd::MessageResp);
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assert(pkt->cmd == MemCmd::WriteResp);
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if (--pendingIPIs == 0) {
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InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
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// Record that the ICR is now idle.
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@@ -84,7 +84,7 @@ namespace X86ISA
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size, Request::UNCACHEABLE,
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Request::intMasterId);
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PacketPtr pkt = new Packet(req, MemCmd::MessageReq);
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PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
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pkt->allocate();
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return pkt;
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}
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@@ -76,7 +76,7 @@ class IntSlavePort : public SimpleTimingPort
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Tick
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recvAtomic(PacketPtr pkt)
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{
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panic_if(pkt->cmd != MemCmd::MessageReq,
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panic_if(pkt->cmd != MemCmd::WriteReq,
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"%s received unexpected command %s from %s.\n",
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name(), pkt->cmd.toString(), getPeer());
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pkt->headerDelay = pkt->payloadDelay = 0;
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